TS52002 Datasheet, PDF (8/14 Pages) List of Unclassifed Manufacturers – High Efficiency NiMH Battery Charger for Photovoltaic Sources

TS52002
Version 1.2
SERIAL INTERFACE
The TS52002 features an I²C slave interface which offers advanced control and diagnostic features. I²C operation offers fault
and warning indicators. Whenever a fault is detected, the associated status bit in the STATUS register is set and the nFLT pin is
pulled low. Whenever a warning is detected, the associated status bit in the STATUS register is set, but the nFLT pin is not
pulled low. Reading of the STATUS register resets the fault and warning status bits, and the nFLT pin is released after all fault
status bits have been reset.
I²C SUBADDRESS DEFINITION
Figure 3: Sub-address in I²C Transmission
I²C BUS OPERATION
The TS52002 has a slave I²C interface that supports standard and fast mode data rates, auto-sequencing, and is compliant to I²C
standard version 3.0.
I²C is a two-wire serial interface where the two lines are serial clock (SCL) and serial data (SDA). SDA must be connected to a
positive supply through an external pull-up resistor. The devices communicating on this bus can drive the SDA line low or
release it to high impedance. The device that initiates the I²C transaction becomes the master of the bus. Communication is
initiated by the master sending a Start condition, a high-to-low transition on SDA, while the SCL line is high. After the Start
condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/nW). After
receiving the valid address byte, the device responds with an acknowledge (ACK). An ACK is a low on SDA during the high of
the ACK related clock pulse. On the I²C bus, during each clock pulse only one data bit is transferred. The data on the SDA line
must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as Start or
Stop control commands. A low-to-high transition on SDA while the SCL input is high, indicates a Stop condition and is sent by
the master (see Figure 4).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each
byte of eight bits is followed by one ACK bit. The SDA line must be released by the transmitter before the receiver can send an
ACK bit. The receiver that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable
low during the high pulse of the ACK-related clock period. When a slave receiver is addressed, it must generate an ACK after
each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. To
ensure proper operation, setup and hold times must be met. An end of data is signaled by the master receiver to the slave
transmitter by not generating an acknowledge after the last byte has been clocked out of the slave. This is done by the master
receiver by holding the SDA line high. The transmitter must then release the data line to enable the master to generate a Stop
condition.
Specifications subject to change
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