SEP02G72D1BH2MT-25R Datasheet, PDF (8/14 Pages) List of Unclassifed Manufacturers – 2GB DDR2 – SDRAM registered DIMM

Data Sheet
Rev.1.2 25.11.2010
Parameter
& Test Condition
Symbol
Max.
6400-666
5300-555
OPERATING WRITE CURRENT *) :
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (I_DD), AL = 0;
t_CK = t_CK (I_DD), t_RAS = t_RAS MAX (I_DD), t_RP = t_RP (I_DD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two
clock cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
t_CK = t_CK (I_DD); refresh command at every t_RFC (I_DD)
interval, CKE is HIGH, CS# is HIGH between valid
commands; All other Control and Address bus inputs
are changing once every two clock cycles; DQ inputs
changing once per clock cycle
SELF REFRESH CURRENT:
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at V_REF; DQ’s are
floating at V_REF
OPERATING CURRENT *) :
Four device bank interleaving READs, I_OUT = 0mA; BL = 4,
CL = CL (I_DD), AL = t_RCD (I_DD) – 1 x t_CK (I_DD); t_CK = t_CK
(I_DD), t_RC = t_RC (I_DD), t_RRD = t_RRD (I_DD), t_RCD = t_RCD (I_DD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during
DESELECT; DQ inputs changing once per clock cycle
I_DD4W
I_DD5
I_DD6
I_DD7
1503
4230
126
3078
1278
3870
126
2583
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P
(CKE LOW) mode.
Unit
mA
mA
mA
mA
TIMING VALUES USED FOR I_DD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
6400-666
5300-555
CL (IDD)
6
5
t_RCD (IDD)
t_RC (IDD)
t_RRD (IDD)
t_CK (IDD)
t_RAS MIN (IDD)
t_RAS MAX
(IDD)
15
60
7.5
2.5
45
70’000
15
60
7.5
3.0
45
70’000
t_RP (IDD)
15
15
t_RFC (IDD)
105
105
Unit
t_CK
ns
ns
ns
ns
ns
ns
ns
ns
Swissbit AG
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CH-9552 Bronschhofen
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www.swissbit.com
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