SEP02G72D1BH2MT-25R Datasheet, PDF (7/14 Pages) List of Unclassifed Manufacturers – 2GB DDR2 – SDRAM registered DIMM

Data Sheet
Rev.1.2 25.11.2010
I_DD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
Parameter
& Test Condition
OPERATING CURRENT *) :
One device bank Active-Precharge;
t_RC= t_RC (I_DD); t_CK = t_CK (I_DD); CKE is HIGH, CS# is
HIGH between valid commands;
DQ inputs changing once per clock cycle; Address
and control inputs changing once every two clock
cycles
OPERATING CURRENT *) :
One device bank; Active-Read-Precharge;
I_OUT = 0mA; BL = 4, CL = CL (I_DD), AL = 0;
t_CK = t_CK (I_DD), t_RC= t_RC (I_DD), t_RAS = t_RAS MIN (I_DD),
t_RCD = t_RCD (I_DD); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as I_DD4W
PRECHARGE POWER-DOWN CURRENT:
All device banks idle; Power-down mode;
t_CK = t_CK (I_DD); CKE is LOW; All Control and Address
bus inputs are not changing; DQ’s are floating at V_REF
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
t_CK = t_CK (I_DD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at V_REF
PRECHARGE STANDBY CURRENT:
All device banks idle;
t_CK = t_CK (I_DD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing
once per clock cycle
ACTIVE POWER-DOWN
CURRENT:
Fast PDN Exit
MR[12] = 0
All device banks open; t_CK = t_CK
(I_DD); CKE is LOW; All Control
Slow PDN Exit
MR[12] = 1
and Address bus inputs are not
changing; DQ’s are floating at
V_REF
ACTIVE STANDBY CURRENT:
All device banks open; t_CK = t_CK (I_DD),
t_RAS = t_RAS MAX (I_DD), t_RP = t_RP (I_DD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing
once per clock cycle
OPERATING READ CURRENT *) :
All device banks open, Continuous burst reads; One
module rank active; I_OUT = 0mA; BL = 4, CL = CL (I_DD),
AL = 0; t_CK = t_CK (I_DD), t_RAS = t_RAS MAX (I_DD), t_RP = t_RP
(I_DD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
Symbol
I_DD0
I_DD1
I_DD2P
I_DD2Q
I_DD2N
I_DD3P
I_DD3N
I_DD4R
max.
6400-666
5300-555
873
828
1053
963
126
126
900
720
900
720
720
540
180
180
1080
990
1503
1278
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
Unit
mA
mA
mA
mA
mA
mA
mA
mA
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