IS62C5128BL-45QLI Datasheet, PDF (8/14 Pages) List of Unclassifed Manufacturers – 512K x 8 HIGH-SPEED CMOS STATIC RAM

IS62C5128BL, IS65C5128BL
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)^(1,2)
ADDRESS
CE
WE
DOUT
DIN
t SA
t WC
VALID ADDRESS
t SCS
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
CE_WR1.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW.All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write.The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ Vih.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  B
06/28/2011