FGLS12SR6040A Datasheet, PDF (8/21 Pages) List of Unclassifed Manufacturers – 4.5-14.4Vdc Input, 40A, 0.6-2.0Vdc Output

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FGLS12SR6040*A
4.5-14.4Vdc Input, 40A, 0.6-2.0Vdc Output
Preliminary Data Sheet
and the VOUT and GND pins of the module should
not exceed 0.5V.
Caution – Do not connect SIG_GND to
GND elsewhere in the layout.
Fig-6: Circuit configuration for programming
output voltage using and external resistor.
Voltage Margining
Output voltage margining can be implemented in the
module by connecting a resistor, Rmargin-up, from
the Trim pin to the ground pin for margining-up the
output voltage and by connecting a resistor,
Rmargin-down, from the Trim pin to output pin for
margining-down. Fig-7 shows the circuit configuration
for output voltage margining. The POL Programming
Tool, available at www.fdk.com under the Downloads
section, also calculates the values of Rmargin-up and
Rmargin-down for a specific output voltage and %
margin. Please consult your local FDK FAE for
additional details.
Without an external resistor between Trim and
SIG_GND pins, the output of the module will be
0.6Vdc. To calculate the value of the trim resistor,
Rtrim for a desired output voltage, should be as per
the following equation:
R _TRIM
12
 _{(VO-REQ - 0.6)}
[kΩ]
Rtrim is the external resistor in k
Vo-req is the desired output voltage
Note that the tolerance of a trim resistor will affect the
tolerance of the output voltage. Standard 1% or 0.5%
resistors may suffice for most applications; however,
a tighter tolerance can be obtained by using two
resistors in series instead of one standard value
resistor.
Table 1 lists calculated values of R_TRIM for common
output voltages.
Table 1: Trim Resistor Value
V_O-REG [V]
0.6
R_TRIM [k]
Open
0.9
40
1.0
30
1.2
20
1.5
13.33
1.8
10
Remote Sense
The power module has a Remote Sense feature to
minimize the effects of distribution losses by
regulating the voltage between the sense pins (VS+
and VS-). The voltage drop between the sense pins
Fig-7: Circuit Configuration for margining Output
Voltage.
Output Voltage Sequencing
The power module includes a sequencing feature,
EZSEQUENCE that enables users to implement
various types of output voltage sequencing in their
applications. This is accomplished via an additional
sequencing pin. When not using the sequencing
feature, leave it unconnected.
The voltage applied to the SEQ pin should be scaled
down by the same ratio as used to scale the output
voltage down to the reference voltage of the module.
This is accomplished by an external resistive divider
connected across the sequencing voltage before it is
fed to the SEQ pin as shown in Fig-8. In addition, a
small capacitor (suggested value 100pF) should be
connected across the lower resistor R1
For all Tomodachi modules, the minimum
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Ver 1.5 May. 9, 2013