FGLS12SR6040A Datasheet, PDF (10/21 Pages) List of Unclassifed Manufacturers – 4.5-14.4Vdc Input, 40A, 0.6-2.0Vdc Output

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FGLS12SR6040*A
4.5-14.4Vdc Input, 40A, 0.6-2.0Vdc Output
Preliminary Data Sheet
interleaved to reduce input ripple/filtering
requirements.
 The share pins of all units in parallel must be
connected together. The path of these
connections should be as direct as possible.
 The remote sense connections to all modules
should be made that to the same points for the
output, i.e. all VS+ and VS- terminals for all
modules are connected to the power bus at the
same points.
Some special considerations apply for design of
converters in parallel operation:
 When sizing the number of modules required for
parallel operation, take note of the fact that
current sharing has some tolerance. In addition,
under transient conditions such as a dynamic
load change and during startup, all converter
output currents will not be equal. To allow for
such variation and avoid the likelihood of a
converter shutting off due to a current overload,
the total capacity of the paralleled system should
be no more than 90% of the sum of the individual
converters. As an example, for a system of four
FGLS converters in parallel, the total current
drawn should be less that 90% of (3 x 40A), i.e.
less than 108 A.
 All modules should be turned ON and OFF
together. This is so that all modules come up at
the same time avoiding the problem of one
converter sourcing current into the other leading
to an overcurrent trip condition. To ensure that all
modules come up simultaneously, the on/off pins
of all paralleled converters should be tied together
and the converters enabled and disabled using
the on/off pin. Note that this means that
converters in parallel cannot be digitally turned
ON as that does not ensure that all modules
being paralleled turn on at the same time.
 If digital trimming is used to adjust the overall
output voltage, the adjustments need to be made
in a series of small steps to avoid shutting down
the output. Each step should be no more than
20mV for each module. For example, to adjust
the overall output voltage in a setup with two
modules (A and B) in parallel from 1V to 1.1V,
module A would be adjusted from 1.0 to 1.02V
followed by module B from 1.0 to 1.02V, then
each module in sequence from 1.02 to 1.04V and
so on until the final output voltage of 1.1V is
reached.
 If the Sequencing function is being used to
start-up and shut down modules and the module
is being held to 0V by the tracking signal then
there may be small deviations on the module
output. This is due to controller duty cycle
limitations encountered in trying to hold the
voltage down near 0V.
 The share bus is not designed for redundant
operation and the system will be non-functional
upon failure of one of the units when multiple
units are in parallel. In particular, if one of the
converters shuts down during operation, the other
converters may also shut down due to their
outputs hitting current limit. In such a situation,
unless a coordinated restart is ensured, the
system may never properly restart since different
converters will try to restart at different times
causing an overload condition and subsequent
shutdown. This situation can be avoided by
having an external output voltage monitor circuit
that detects a shutdown condition and forces all
converters to shut down and restart together.
When not using the active load share feature, share
pins should be left unconnected.
Power Good
The module provides a Power Good (PGOOD) signal
that is implemented with an open-drain output to
indicate that the output voltage is within the regulation
limits of the power module. The PGOOD signal will be
de-asserted to a low state if any condition such as
over-temperature, overcurrent or loss of regulation
occurs that would result in the output voltage going
outside the specified thresholds.
The default value of PGOOD ON thresholds are set at
±8% of the nominal Vset value, and PGOOD OFF
thresholds are set at ±10% of the nominal Vset. For
example, if the nominal voltage (Vset) is set at 1.0V,
then the PGOOD ON thresholds will be active
anytime the output voltage is between 0.92V and
1.08V, and PGOOD OFF thresholds are active at
0.90V and 1.10V respectively.
The PGOOD terminal can be connected through a
pull-up resistor (suggested value 100K) to a source
of 5VDC or lower.
Dual Layout
Identical dimensions and pin layout of Analog and
Digital Tomodachi modules permit migration from
one to the other without needing to change the layout.
In both cases the trim resistor is connected between
trim and signal ground SIG_GND.
Tunable Loop™
The module has a feature that optimizes transient
response of the module called Tunable Loop™
External capacitors are usually added to the output of
the module for two reasons: to reduce output ripple
and noise and to reduce output voltage deviations
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Ver 1.5 May. 9, 2013