EM351 Datasheet, PDF (78/240 Pages) List of Unclassifed Manufacturers – High-Performance, Integrated ZigBee/802.15.4 System-on-Chip

EM351 / EM357
The GPIO pins used for these signals are shown in Table 8-3. Additional outputs may be needed to drive the
nSSEL signals on slave devices.
Direction
GPIO Configuration
SC1 pin
SC2 pin
Table 8-3. SPI Master GPIO Usage
MOSI
MISO
Output
Input
Alternate Output
(push-pull)
Input
PB1
PB2
PA0
PA1
SCLK
Output
Alternate Output
(push-pull)
PB3
PA2
8.3.2 Set Up and Configuration
Both serial controllers, SC1 and SC2, support SPI master mode. SPI master mode is enabled by the following
register settings:
ƒ ^{The serial controller mode register (SCx_MODE) is 2.}
ƒ ^{The SC_SPIMST bit in the SPI configuration register (SCx_SPICFG) is 1.}
The SPI serial clock (SCLK) is produced by a programmable clock generator. The serial clock is produced by
dividing down 12 MHz according to this equation:
rate = ^12MHz
(LIN + 1) * 2^EXP
EXP is the value written to the SCx_RATEEXP register and LIN is the value written to the SCx_RATELIN register.
The SPI master mode clock may not exceed 12 Mbps, so EXP and LIN cannot both be zero.
The SPI master controller supports various frame formats depending upon the clock polarity (SC_SPIPOL),
clock phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see Table 8-4). The bits SC_SPIPOL, SC_SPIPHA,
and SC_SPIORD are defined within the SCx_SPICFG register.
8-7
Preliminary
120-035X-000D