EM351 Datasheet, PDF (100/240 Pages) List of Unclassifed Manufacturers – High-Performance, Integrated ZigBee/802.15.4 System-on-Chip

EM351 / EM357
8.6.7 Registers
Refer to Registers (in the SPI Master Mode section) for a description of the SCx_DATA register.
SC1_UARTSTAT
UART Status Register
Address: 0x4000C848 Reset: 0x40
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
SC_UARTTXIDLE
SC_UARTPARERR SC_UARTFRMERR SC_UARTRXOVF
SC_UARTTXFREE
SC_UARTRXVAL
SC_UARTCTS
Bitname
SC_UARTTXIDLE
SC_UARTPARERR
SC_UARTFRMERR
SC_UARTRXOVF
SC_UARTTXFREE
SC_UARTRXVAL
SC_UARTCTS
Bitfield
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Access
R
R
R
R
R
R
R
Description
This bit is set when both the transmit FIFO and the transmit serializer are empty.
This bit is set when the byte in the data register was received with a parity error. This bit
is updated when the data register is read, and is cleared if the receive FIFO is empty.
This bit is set when the byte in the data register was received with a frame error. This bit
is updated when the data register is read, and is cleared if the receive FIFO is empty.
This bit is set when the receive FIFO has been overrun. This occurs if a byte is received
when the receive FIFO is full. This bit is cleared by reading the data register.
This bit is set when the transmit FIFO has space for at least one byte.
This bit is set when the receive FIFO contains at least one byte.
This bit shows the logical state (not voltage level) of the nCTS input:
0: nCTS is deasserted (pin is high, 'XOFF', RS232 negative voltage); the UART is inhibited
from starting to transmit a byte.
1: nCTS is asserted (pin is low, 'XON', RS232 positive voltage); the UART may transmit.
8-29
Preliminary
120-035X-000D