TLA7SA00 Datasheet, PDF (7/14 Pages) List of Unclassifed Manufacturers – Tektronix PCI Express Logic Protocol Analyzer

TLA7SA00 Logic Protocol Analyzer Datasheet
Acquisition system (with P67SA00 series probes)
Dynamic link width switch latency Consumes up to 48 symbols (typical)
Dynamic link rate switch latency
Maximum time to change to
Gen1 rate
Maximum time to change to
Gen2 rate
Maximum time to change to
Gen3 rate
<200 ns EIDLE time (typical) (with either internal reference clock or spread spectrum using external reference clock)
2 TS1
1 EIEOS + 3 TS1
1 EIEOS + 6 TS1
Number of FTS packets required to Assumes an EIDLE ranging from 20 ns to 2 ms, with either internal reference clock or spread spectrum using external reference
resync following L0s exit
clock
Gen1
4 FTS (typical)
Gen2
1 EIEOS + 6 FTS (typical)
Gen3
1 EIEOS + 4 FTS (typical)
Filter specifications
Ordered sets
DLLPs
TLPs
TS1, TS2, SKP, EIOS, FTS, EIEOS, SDS
Ack, Nak, PM, Vendor specific, FC1, FC2, UpdateFC
MRd, MRdL, MWr, IORd, IOWr, CfgRd0, CfgWr0, CfgRd1, CfgWr1, Msg, MsgD, Cpl, CplD, CPlLk, CPlDLk, FetchAdd, Swap,
CAS, LPrfx, EPrfx
Trigger system
Independent Trigger states
8
Trigger sequence rate
Operates at symbol rate time (Gen1, Gen2, Gen3)
Maximum independent If/Then
8
clauses per state
Maximum number of events per If/ 8
Then clause
Maximum number of actions per If/ 8
Then clause
Maximum number of event
2
counters per state
Event counter range
31 bit
Number of TLP packet recognizers 4
per link direction
Number of DLLP packet
4
recognizers per link direction
Number of sequence recognizers 4
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