ARM720T Datasheet, PDF (68/242 Pages) List of Unclassifed Manufacturers – General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip

Configuration
3.3.5
Register 4, reserved
Register 4 is reserved. Reading CP15 register 4 is unpredictable. Writing CP15 register
4 is unpredictable. This is shown in Figure 3-8.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
UNP
Figure 3-8 Register 4
3.3.6
Register 5, fault status register
Reading CP15 register 5 returns the value of the Fault Status Register (FSR). The FSR
contains the source of the last data fault.
Note
Only the bottom 9 bits are returned. The upper 23 bits are unpredictable.
The FSR indicates the domain and type of access being attempted when an abort
occurred:
Bit 8
This is always read as zero. Bit 8 is ignored on writes.
Bits [7:4]
These specify which of the 16 domains (D15-D0) was being
accessed when a fault occurred.
Bits [3:1]
Theses indicate the type of access being attempted.
The encoding of these bits is shown in Fault address and fault status registers on
page 6-19. The FSR is only updated for data faults, not for prefetch faults.
Writing CP15 register 5 sets the FSR to the value of the data written. This is useful when
a debugger has to restore the value of the FSR. The upper 24 bits written should be zero.
The CRm and opcode_2 fields should be zero when reading or writing CP15 register 5.
Register 5 is shown in Figure 3-9.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
UNP/SBZ
0 Domain Status
Figure 3-9 Register 5
3-8
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ARM DDI 0192A