ARM720T Datasheet, PDF (66/242 Pages) List of Unclassifed Manufacturers – General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip

Configuration
3-6
C Bit 2
W Bit 3
P Bit 4
D Bit 5
L Bit 6
B Bit 7
S Bit 8
R Bit 9
Bits 12:10
Cache enable/disable:
0 = Instruction and/or Data Cache (IDC) disabled
1 = Instruction and/or Data Cache (IDC) enabled.
Write buffer enable/disable:
0 = Write Buffer disabled
1 = Write Buffer enabled.
When read, returns 1. When written, is ignored.
When read, returns 1. When written, is ignored.
When read, returns 1. When written, is ignored.
Big-endian/little-endian:
0 = Little-endian operation
1 = Big-endian operation.
System protection:
Modifies the MMU protection system.
ROM protection:
Modifies the MMU protection system.
When read, this returns an unpredictable value. When written, it
should be zero, or a value read from these bits on the same
processor.
Note
Using a read-write-modify sequence when modifying this register provides the greatest
future compatibility.
V Bit 13
Bits 31:14
Location of exception vectors:
0 = low addresses
1 = high addresses.
When read, this returns an unpredictable value. When written, it
should be zero, or a value read from these bits on the same
processor.
Enabling the MMU
You must take care if the translated address differs from the untranslated address,
because the instructions following the enabling of the MMU are fetched using no
address translation. Enabling the MMU can be considered as a branch with delayed
execution.
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ARM DDI 0192A