ALS300 Datasheet, PDF (61/66 Pages) List of Unclassifed Manufacturers – Media Audio Controller SPEC

Avance Logic Inc.
ALS300
ALS300 implemented DDMA register for system chipset access. The DDMA address is
calculated as follow :
DDMABASE[31..16]=0
DDMABASE[15..6]=GCR99.15~6
DDMABASE[5..4]= 00 SBDMA=000
01 SBDMA=001
11 SBDMA=011
DDMABASE[3..0] map to the following operation.
DDMABASE[3..0] Type
Function
00h
W
SBDMA=000 Write to GCR91.7~0
SBDMA=001 Write to GCR93.7~0
SBDMA=011 Write to GCR95.7~0
00h
R
Read from CA.7~0
01h
W
SBDMA=000 Write to GCR91.15~8
SBDMA=001 Write to GCR93.15~8
SBDMA=011 Write to GCR95.15~8
01h
R
Read from CA.15~8
02h
R/W
SBDMA=000 Access GCR91.23~16
SBDMA=001 Access GCR93.23~16
SBDMA=011 Access GCR95.23~16
03h
Reserved
04h
W
SBDMA=000 Write to GCR92.7~0
SBDMA=001 Write to GCR94.7~0
SBDMA=011 Write to GCR96.7~0
04h
R
Read from CBC.7~0
05h
W
SBDMA=000 Write to GCR92.15~8
SBDMA=001 Write to GCR94.15~8
SBDMA=011 Write to GCR96.15~8
05h
R
Read from CBC.15~8
06h~07h
Reserved
08h
W
Write bit 2 to GCR98.14
08h
R
Read internal DMA status
09h
W
Terminate the cycle only
0Ah
Reserved
0Bh
W
SBDMA=000 Write bit5~2 to GCR92.21~18
SBDMA=001 Write bit5~2 to GCR94.21~18
SBDMA=011 Write bit5~2 to GCR96.21~18
0Ch
Reserved
0Dh
W
Clear FFLP,DMA group enable(GCR98.14),DMA status and
set mask bit (GCR98.31,29,28)
0E
Reserved
0F
W
SBDMA=000 Write bit 0 to GCR98.28
SBDMA=001 Write bit 0 to GCR98.29
SBDMA=011 Write bit 0 to GCR98.31
For DMA compatibility issue, CA/CBC load starting value according the condition as follow :
Source
Enabled condition
GCR91
(SBDMA=0)&[(write PNP0-74) | (IO write GCR91,GCR92.15~0)
GCR92
| (TC=1 in auto-initialization mode)]
GCR93
(SBDMA=1)&[(write PNP0-74) | (IO write GCR93,GCR94.15~0)
GCR94
| (TC=1 in auto-initialization mode)]
GCR95
(SBDMA=3)&[(write PNP0-74) | (IO write GCR95,GCR96.15~0)
GCR96
| (TC=1 in auto-initialization mode)]
Note : TC=1 when CBC reach FFFFh.
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