ALS300 Datasheet, PDF (59/66 Pages) List of Unclassifed Manufacturers – Media Audio Controller SPEC

Avance Logic Inc.
ALS300
Appendix A : PnP and DMA Emulation
PNP state :
PNP state
PNPS[1..0]
Wait-for-key
00
Sleep
01
Configuration
10
Isolation
11
The PnP specification define PnP register indexed 00h~2Fh as card level register, others as
device level register. For simplicity, we define
PNPxx
: PNP card level register xx, where xx is in range of 00h to 2fh.
PNPy-xx
: PNP device y register xx, where xx is in range of 30h to ffh
Note that PNPxx and PNPy-xx implemented in PCI interface are write-only for PnP
compatibility. The write operation is enabled only when PNPS[1..0]=1x.
ALS300 “PnP emulation block” decode the following address range for “SB logic” when
GCR9A.1=0 :
Address
Length
Type
Enabled condition
SBBASE[15..0]
16 bytes
IO R/W
(PNP0-30.0=1)|(PNP0.31.1=1)
OPLBASE[15..0]
4 bytes
IO R/W
(PNP1-30.0=1)|(PNP1-31.1=1)
GAMEBASE[15..0]
8 bytes
IO R/W
(PNP2-30.0=1)|(PNP2-31.1=1)
MPUBASE[15..0]
4 bytes
IO R/W
(PNP3-30.0=1)|(PNP3-31.1=1)
279h
1 byte
IO W
*Note*
A79h
1 byte
IO W
*Note*
RA[9..0]
1 byte
IO R
n Note : ALS300 claim write cycle of A79h only when
PNPS[1..0]=[1x]
[(PNPS[1..0]=01) & CSN0&(PNP index = 03)]
where CSN0 is the flag indicating CSN=0. CSN0=1 means CSN = 0.
For other conditions, ALS300 “snoop” it only. Remember that ALS300 always
forward write cycle of A79h to SB logic.
oFor 279h decoding, ALS300 always snoop and forward to SB core logic.
pFor PnP read port decoding, ALS300 snoop and forward to SB logic only when
PNPS[1..0]=1x.
DMA emulation by BUS Master function :
ALS300 implement 2 types of DMA emulation scheme : Legacy DMA and Distributed DMA
(DDMA). ALS300 emulate the assigned channel (0,1,3) only.
Internal Registers/Flags :
RETRYThe flag decide whether read status from 8237 or not.(Effective in Legacy-DMA)
1
Enabled read (Default)
0
Disable read
FFLP 1_bit Flip-Flop function as low/high byte pointer for DMA IO register (00~07h)
(Effective in Legacy-DMA)
Write 0x0c will clear FFLP to 0.FFLP is default 0 after reset. Any access to
00h~07h will toggle it‘s value.
CA
24-bit address counter of DMA emulation.
CBC
16-bit byte counter of DMA emulation.
zDMA Emulation Scheme for Legacy-DMA mode and DDMA mode :
Legacy-DMA Mode :
ALS300 decode the following IO command :
Address Command
Function
Enabled
00h IO write
FFLP=0: Write to GCR91.7~0
Always
FFLP=1: Write to GCR91.15~8
00h IO read
FFLP=0: read from CA.7~0
SBDMA
FFLP=1: read from CA.15~8
= 000
01h IO write
FFLP=0: Write to GCR92.7~0
Always
FFLP=1: Write to GCR92.15~8
01h IO read
FFLP=0: read from CBC.7~0
SBDMA
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