T-51638D084-FW-A-AA Datasheet, PDF (6/17 Pages) –

PRELIMINARY
5. INTERFACE TIMING
(1) Timing Specifications
ITEM
SYMBOL
Frequency
DCLK
Period
Low Width
High Width
DATA _{Set up time}
(R,G,B,DENA,
HD, VD) Hold time
Horizontal Active Time
Horizontal Front Porch
DENA
Horizontal Back Porch
Vertical Active Time
Vertical Front Porch
Vertical Back Porch
Frequency
HD
Period
Low Width
Frequency
VD
Period
Low Width
f_CLK
t_CLK
t_WCL
t_WCH
t_DS
t_DH
t_HA
t_HFP
t_HBP
t_VA
t_VFP
t_VBP
f_H
t_H
t_WHL
f_V
t_V
t_WVL
MIN.
20
33.3
10
10
5
5
640
0
7
480
1
8
27
26.3
5
55
14.2
2
TYP.
25
40
--
--
--
--
640
16
144
480
10
35
31.5
31.7
96
60
16.7
2
MAX.
30
50
--
--
--
--
640
--
--
480
--
--
38
37.0
--
70
18.2
--
UNIT
MHz
ns
ns
ns
ns
ns
t_CLK
t_CLK
t_CLK
t_H
t_H
t_H
kHz
ms
t_CLK
Hz
ms
t_H
[Note]
1) DATA is latched at fall edge of DCLK in this timing specification.
2) Polarities of HD and VD are negative in this specification.
3) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
4) DCLK should appear during all invalid period, and HD should appear during invalid period of
frame cycle.
T-51638D084-FW-A-AA
OPTREX CORPORATION
Page 6/17