EAEDIP128B-6LW Datasheet, PDF (6/29 Pages) List of Unclassifed Manufacturers – OPERATING UNIT 128x64 with touch panel

EA eDIP128-6
Page 6
ELECTRONIC ASSEMBLY reserves
the right to change specifications
without prior notice. Printing and
typographical errors reserved.
SPI INTERFACE
If the display is wired as shown
below, SPI mode is activated.
The data is then transferred via
the serial, synchronous SPI
interface.
The transfer parameter will be set
via the pins DORD, CPOL and
CPHA.
Pinout eDIP128-6: SPI mode
Pin Symbol In/Out Function
Pin Symbol In/Out Function
1 GND
Ground Potential for logic (0V)
17 DPROT
In
L: Disable Smallprotokoll
do not connect for normal operation
2 VDD
Power supply for logic (+3,3V..5V)
18 PWR
Out
L: Normal Operation
H: Powerdownmode
3 NC
do not connect
19 NC
do not connect
4 NC
do not connect
20
TEST
SBUF
In
Out
open-drain with internal pullup 20k..50k
IN (Power-On) L: Testmode
OUT L: data in sendbuffer
5 RESET In L: Reset
21 GND
Ground (0V)
6 SS
In Slave Select
22 VDD
Power supply (+3,3..5V)
7 MOSI In Serial In
23 NC
do not connect
8 MISO Out Serial Out
24 NC
do not connect
9 CLK In Shift Clock
25 IN8/OUT1
10 DORD In Data Order (0=MSB first; 1=LSB first)
11 SPIMOD In connect to GND for SPI interface
12 NC
do not connect
26 IN7/OUT2
27 IN6/OUT3
28 IN5/OUT4
8 digital inputs
(internal 20k..50k pullup)
13 WUP
14 CPOL
15 CPHA
In
L: (Power-On) disable Power-On-Macro
L: Wakeup from Powerdownmode
In Clock Polarity (0=LO 1=HI when idle)
In Clock Phase sample 0=1st;1=2nd edge
29 IN4/OUT5
30 IN3/OUT6
31 IN2/OUT7
alternativ up to 8 digital outputs
maximum current:
IOL = IOH = 10mA
16 BUZZ Out Buzzer output
32 IN1/OUT8
Note:
The pins DORD, CPOL, CPHA, DPOM, DPROT and TEST/SBUF have an internal pullup, which is why only the LO level
(0=GND) is to be actively applied. These pins must be left open for a hi level.
On pin 20 (SBUF) the display indicates with a low level that data is ready to be retrieved from the internal send buffer.
The line can be connected to an interrupt input of the host system, for example.
DATATRANSFER SPI
Write operation: a clock rate up to 100 kHz is allowed
without any stop. Together with a pause of 100 µs
between every data byte a clock rate up to 3 MHz can
be reached.
Read operation: to read data (e.g. the „ACK“ byte) a
dummy byte (e.g . 0xFF) need to be sent.
Note that the EA eDIP for internal operation does need
a short time before providing the data; therefore a short
pause of min. 6µs (no activity of CLK line) is needed for
each byte.
Application note