CC1010 Datasheet, PDF (59/133 Pages) Texas Instruments – Single Chip Very Low Power RF Transceiver with 8051-Compatible Microcontroller

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SmartRF ^â CC1010
System clock
Clear
Enable
Watchdog Prescaler
WDTCLR
Clear
Enable
8 Bit Watchdog Counter
WDTPRE(1:0)
WDTEN
System
Reset
Figure 14. Watchdog Timer
Setting different prescaler settings,
combined with different Main Crystal
Oscillator frequencies, generates reset at
an interval of:
256 ⋅ 2^(11+WDTPRE)
f _system
The intervals for the maximum and
minimum clock frequencies are shown in
Table 15 below.
Table 15. Watchdog Timer timing
WDTPRE.1 WDTPRE.0 Division Rate
0
0
0
1
1
0
1
1
2048
4096
8192
16384
Reset timing, given
fXOSC = 3MHz
175 ms
350 ms
699 ms
1400 ms
Reset timing, given
fXOSC = 24MHz
21.8 ms
43.7 ms
87.4 ms
175 ms
Disabling the Watchdog Timer
The Watchdog Timer is enabled after
system reset, through the Watchdog Timer
enable flag WDT.WDTEN. To disable the
Watchdog Timer, this flag must be
cleared. However, clearing this flag
requires the user to first set the flag
WDT.WDTSE, and then clearing
WDT.WDTEN within 16 system clock
periods (preferably in the next instruction).
If interrupts are enabled while disabling
the Watchdog Timer, the user must make
sure that WDT.WDTEN is actually cleared.
This could for instance be done as follows:
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SmartRF^â CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 59 of 133