GM5020 Datasheet, PDF (55/86 Pages) List of Unclassifed Manufacturers – Graphics Processing IC providing high-quality images for LCD monitors and other pixelated displays

Genesis Microchip
gm5020 / gm5020-H Data Sheet
4.13 Display Timing and Control
Analog
RGB
Triple
ADC
Clock
Recovery
Digital
DVI
DVI
Rx
Digital YUV
Video
ITU656
(8-bits) Decoder
HDCP
.
Serial
Interface
SDRAM
Interface
Image
Capture
Host
Interface
Micro-
processor
(MCU)
Frame
Store
Interface
YUV
RealColor
Controls
RGB
Color
Controls
Input
Color
LUT
Frame Rate
Conversion
Image
Measurement
OSD
Zoom/
Shrink
Scaling
Gamma
Correction
LUT
Panel
Display Timing Interface
& Control
(24/48-bits)
Display
Clock
Generation
Figure 37. Display Timing and Control Blocks
The Display Output Port provides data and control signals that permit the gm5020 to connect to a
variety of flat panel or CRT devices. The output interface is configurable for 18 or 24-bit RGB
pixels, either single or double pixel wide. All display data and timing signals are synchronous
with the DCLK output clock.
4.13.1 Display Clock Generation – Display Digital Direct Synthesis Block (DDDS)
The Display DDS is responsible for generating the display clock frequency. The DDDS can
operate in two different configurations: Open loop and Closed Loop FRD (Frequency Ratio
Detector) method. The implementation of the DDDS is shown in the following diagram:
10 MHz <= DDDS_CLK <= 30 MHz
40 MHz <= Fout <= 330 MHz
10 MHz <= DCLK <= 135 MHz
IP_CLK
FRD
DDDS_CLK
DDDS
PFD
Filter
Fout
VCO
Output Divider
Divide by:
2^OUT_DIV
(Divide by 1 if
OUT_DIV = 0)
DCLK
RCLK
PLL Divider
Divide by:
(PLL_DIVDE + 1)
PLL Prescaler
Divide by:
(Prescale_En + 1)
Figure 38. DDDS Block
February 2002
46
C5020-DAT-01Q