GM5020 Datasheet, PDF (26/86 Pages) List of Unclassifed Manufacturers – Graphics Processing IC providing high-quality images for LCD monitors and other pixelated displays

Genesis Microchip
gm5020 / gm5020-H Data Sheet
4.2 Hardware and Software Resets
4.2.1 Hardware Reset
Hardware Reset is performed by holding the RESETn pin low for a minimum of 1µs after the
supply voltages are stable, as illustrated in Figure 9. A TCLK input (see Clock Options above)
must be applied during and after the reset. When the reset period is complete and RESETn is de-
asserted, the gm5020 follows an internal power up sequence:
1. All registers of all types are reset to their default state
2. Each clock domain is internally reset. The reset period remains asserted for 64 local clock
domain cycles following the de-assertion of RESETn.
3. The OCM_CLK domain operates at the T_CLK frequency during this period.
4. The RCLK PLL internally produces a 10x output clock (from TCLK reference).
5. The IC will wait for RCLK PLL to Lock and then switch the OCM_CLK to the bootstrap
selected clock.
6. The OCM will begin operating if bootstrapped to start operation after Hardware Reset,
otherwise it remains in reset until register enabled.
4.2.2 Software Reset
Software Reset is performed by programming the HOST_CONTROL register bit SOFT_RESET
= ’0’. The SOFT_RESET bit will self clear to ‘0’ upon completion of reset. The following
internal operations occur with software reset:
1. All active and status registers (i.e. the active part of PA bits, and CRO and RO bits unless
otherwise indicated) are reset to their default state. Pending and read/write registers remain
unaffected. PA, CRO, and RO bits are defined below:
PA
CRO
RO
Pending and active read write bit. Two registers are used to store these bits: a pending register and
an active register. The pending register is transferred to the active register on an update event. The
clock domain for each PA register is indicated within square brackets ‘[ ]’ in the register listing (e.g. the
active part of register 0x1B6 DISPLAY_CONTROL PA [DP_CLK] will be updated on an update event
synchronized to the rising edge of DP_CLK.)
Only the active register contents affect chip functionality. The active register bits are cleared to ‘0’,
unless otherwise specified, by software or hardware reset. The pending register bits are only cleared
by a hardware reset, and may be overwritten at any time.
Clearable read only status bit. These are read only registers that may be cleared to ‘0’ when
overwritten with a ‘1’. This type is most commonly used for interrupt status registers. These are
cleared to ‘0’ by both software and hardware reset.
Read only status bit. These are read only registers. No effect to the chip will occur if an attempt is
made to write to these bits
2. Each clock domain in the gm5020 is internally reset for 64 local clock domain cycles, before
returning to normal operation.
Software Reset will NOT reset the analog components of the RCLK PLL, FCLK PLL, SDDS,
DDDS, DVI, or ADC blocks. Software reset does not affect the IFM.
February 2002
17
C5020-DAT-01Q