LM3S8738 Datasheet, PDF (511/545 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8738 Microcontroller
22.2.5
22.2.6
Parameter Parameter Name
INL
Integral nonlinearity
DNL
Differential nonlinearity
OFF
Offset
GAIN
Gain
a. t_ADC= 1/f_{ADC clock}
Analog Comparator
Min Nom Max Unit
- - ±1 LSB
- - ±1 LSB
- - ±1 LSB
- - ±1 LSB
Table 22-10. Analog Comparator Characteristics
Parameter Parameter Name
Min Nom Max Unit
V_OS
V_CM
C_MRR
T_RT
T_MC
Input offset voltage
- ±10 ±25 mV
Input common mode voltage range
Common mode rejection ratio
0 - V_DD-1.5 V
50 -
- dB
Response time
--
1 µs
Comparator mode change to Output Valid - -
10 µs
Table 22-11. Analog Comparator Voltage Reference Characteristics
Parameter Parameter Name
Min Nom Max Unit
R_HR Resolution high range
- V_DD/32 - LSB
R_LR Resolution low range
- V_DD/24 - LSB
A_HR Absolute accuracy high range -
- ±1/2 LSB
A_LR Absolute accuracy low range -
- ±1/4 LSB
I²C
Table 22-12. I²C Characteristics
Parameter No. Parameter Parameter Name
Min Nom Max
Unit
I1^a
t_SCH Start condition hold time
36 -
-
system clocks
I2^a
t_LP
Clock Low period
36 -
-
system clocks
I3^b
t_SRT I2CSCL/I2CSDA rise time (V_IL =0.5 V to V _IH =2.4 V) - - (see note b)
ns
I4^a
t_DH Data hold time
2-
-
system clocks
I5^c
t_SFT I2CSCL/I2CSDA fall time (V_IH =2.4 V to V _IL =0.5 V) - 9
10
ns
I6^a
t_HT Clock High time
24 -
-
system clocks
I7^a
t_DS Data setup time
18 -
-
system clocks
I8^a
t_SCSR Start condition setup time (for repeated start condition 36 -
-
system clocks
only)
I9^a
t_SCS Stop condition setup time
24 -
-
system clocks
a. Values depend on the value programmed into the TPR bit in the I²C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I ²C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
June 14, 2007
511
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