LM3S8738 Datasheet, PDF (438/545 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
17.1
Block Diagram
Figure 17-1. Ethernet Controller Block Diagram
Interrupt
Interrupt
Control
MACISR
MACIACK
MACIMR
System Clock
Timer
Support
MACTSR
Individual
Address
MACIAR0
MACIAR1
Receive
Control
MACRCR
MACNPR
Data
Access
MACDR
Transmit
Control
MACTCR
MACITHR
MACTRR
MII
Control
MACMCR
MACMDVR
MACMAR
MACMDTX
MACMDRX
Transmit
FIFO
Transmit
Encoding
Collision
Detect
Pulse
Shaping
Carrier
Sense
Receive
FIFO
Receive
Decoding
Clock
Recovery
TXOP
TXON
MDIX
RXIP
RXIN
Media Independent Interface
Management Register Set
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR16
MR17
MR18
MR19
MR23
MR24
Auto
Negotiation
XTLP
Clock
Reference XTLN
17.2
Functional Description
As illustrated in Figure 17-2 on page 438, the Ethernet Controller is functionally divided into two layers
or modules - the Media Access Controller (MAC) layer and Network Physical (PHY) layer. These
correspond to the OSI model layers 2 and 1. The primary interface to the Ethernet controller is a
simple bus interface to the MAC layer. The MAC layer provides transmit and receive processing for
ethernet frames. The MAC layer also provides the interface to the PHY module via an internal Media
Independent Interface (MII).
Figure 17-2. Ethernet Controller
Cortex M3
Ethernet Controller
Media Access Physical
Controller Layer Entity
MAC
(Layer 2)
PHY
(Layer 1)
Magnetics
RJ45
17.2.1
Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3V supply. Failure to connect this pull-up resistor will prevent
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer will auto-negotiate the link parameters by default.
438
June 14, 2007
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