ICS94201 Datasheet, PDF (5/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94201
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description
PWD
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
Bit2 Bit7 Bit6 Bit5 Bit4 _{VCO/REF VCO VCO/ CPUCLK SDRAM}
FS4 FS3 FS2 FS1 FS0 ^{Divider MHz CPU MHz MHz}
0 0 0 0 0 501/18 398.52 6 66.43 99.65
0 0 0 0 1 352/14 360.00 6 60.00 90.00
0 0 0 1 0 504/18 400.91 6 66.80 100.20
0 0 0 1 1 315/11 410.02 6 68.33 102.50
0 0 1 0 0 440/15 420.00 6 70.00 105.00
0 0 1 0 1 440/14 450.00 6 75.00 112.50
0 0 1 1 0 503/15 480.14 6 80.00 120.00
0 0 1 1 1 313/9 497.95 6 83.00 124.50
0 1 0 0 0 515/37 199.29 2 99.65 99.65
0 1 0 0 1 440/35 180.29 2 90.00 90.00
0 1 0 1 0 518/37 200.45 2 100.23 100.23
0 1 0 1 1 446/31 206.00 2 103.00 103.00
0 1 1 0 0 484/33 210.00 2 105.00 105.00
0 1 1 0 1 507/33 219.98 2 110.00 110.00
0 1 1 1 0 514/32 229.99 2 115.00 115.00
0 1 1 1 1 447/16 400.01 2 200.00 200.00
1 0 0 0 0 501/18 398.52 3 132.86 132.86
1 0 0 0 1 454/13 500.03 3 166.67 166.67
1 0 0 1 0 504/18 400.91 3 133.64 133.64
1 0 0 1 1 488/17 411.02 3 137.00 137.00
1 0 1 0 0 440/15 420.00 3
1 0 1 0 1 395/13 435.05 3
1 0 1 1 0 440/14 450.00 3
1 0 1 1 1 503/15 480.14 3
1 1 0 0 0 501/18 398.52 3
1 1 0 0 1 454/13 500.03 3
1 1 0 1 0 504/18 400.91 3
1 1 0 1 1 488/17 411.02 3
1 1 1 0 0 440/15 420.00 3
1 1 1 0 1 395/13 435.05 3
1 1 1 1 0 440/14 450.00 3
1 1 1 1 1 503/15 480.14 3
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
0- Normal
1- Spread spectrum enable ± 0.35% Center Spread
140.00
145.00
150.00
160.00
132.86
166.67
133.64
137.00
140.00
145.00
150.00
160.00
140.00
145.00
150.00
160.00
99.65
125.00
100.23
102.75
105.00
108.75
112.50
120.00
0- Running
1- Tristate all outputs
3V66 PCICLK IOAPIC
MHz MHz MHz
66.43
60.00
66.80
68.33
70.00
75.00
80.00
83.00
66.43
60.00
66.84
68.67
70.00
73.33
76.67
133.33
66.43
83.34
66.82
68.50
70.00
72.50
75.00
80.00
66.93
83.34
66.82
68.50
70.00
72.50
75.00
80.00
33.21
30.00
33.40
34.17
35.00
37.50
40.00
41.50
33.21
30.00
33.41
34.33
35.00
36.67
38.33
66.66
33.21
41.67
33.41
34.25
35.00
36.25
37.50
40.00
33.21
41.67
33.41
34.25
35.00
36.25
37.50
40.00
16.61
15.00
16.70
17.08
17.50
18.75
20.00
20.75
16.61
15.00
16.70
17.17
17.50
18.33
19.17
33.33
16.61
20.83
16.70
17.13
17.50
18.13
18.75
20.00
16.61
20.83
16.7
17.13
17.50
18.13
18.75
20.00
Note 1
0
1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
5