ICS94201 Datasheet, PDF (4/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94201
Brief I²C registers description for ICS94201
Programmable System Frequency Generator
R egister Name
Byte D escription
Pwd Default
Functionality & Frequency Select
Register
0
Output frequency, hardware / I²C frequency
select, spread spectrum & output enable
See individual byte
des cription
control register.
Output Control Registers
1-5 Active / inactive output control registers.
See individual byte
des cription
W riting to this register will configure byte
Byte Count Read Back Register
Latched Inputs Read Back
Register
6
count and how many byte will be read back.
06_H
Do not write 00_H to this byte.
7
The inverse of the latched inputs level could See individual byte
be read back from this register.
des cription
W atchdog enable, watchdog status and
W atchdog Control Registers
8 Bit[6:0] programmable 'safe' frequency' can be
0 0 0 ,0 0 0 0
configured in this register.
This bit selects whether the output
VCO Control Selection Bit
8 Bit[7] frequency is controled by hardware/byte 0
0
configurations or byte 14&15 programming.
W riting to this register will configure the
W atchdog Timer Count Register
9
number of seconds for the watchdog timer
FF_H
to reset.
ICS Reserved Register
10
This is an unused register. W riting to this
register will not affect device functionality.
00_H
Device ID, Vendor ID & Revision ID
Regis ters
11-12
Byte 11 bit[3:0] is ICS vendor id - 0001.
Other bits in these 2 registers designate
device revision ID of this part.
See individual byte
des cription
ICS Reserved Register
13
Don't write into this register, writing 1's will
cause malfunction.
00_H
These registers control the dividers ratio
Depend on
VCO Frequency Control Registers 14-15 into the phase detector and thus control the hardware/byte 0
VCO output frequency.
c o n fi g u ra ti o n
Spread Spectrum Control
Regis ters
16-17
These registers control the spread
percentage amount.
Depend on
hardware/byte 0
c o n fi g u ra ti o n
Output Dividers Control Registers
18-20
Changing bits in these registers result in
frequency divider ratio changes. Incorrect
configuration of group output divider ratio
can cause system malfunction.
Depend on
hardware/byte 0
c o n fi g u ra ti o n
Group Skews Control Registers
21-23
Increment or decrement the group skew
amount as compared to the initial skew.
See individual byte
des cription
Output Rise/Fall Time Select
Regis ters
24
These registers will control the group rise
and fall time.
See individual byte
des cription
Notes:
1. The ICS clock generator is a slave/receiver, I²C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to read back is defined
by writing to byte 6.
2. When writing to bytes 14 - 15, bytes 16 - 17 and bytes 18 - 20, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4. The input is operating at 3.3V logic levels.
5. The data byte format is 8-bit bytes.
6. To simplify the clock generator I²C interface, the protocol is set to use only Block-Writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
7. At power-on, all registers are set to a default condition, as shown.
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