C6845 Datasheet, PDF (5/6 Pages) List of Unclassifed Manufacturers – CRT Controller Megafunction

CAST C6845 Megafunction Datasheet
Start Address
Start Address Register R12 and R13 indicate the first address the Linear Address Generator puts on the Refresh
Memory Address bus at the start of a vertical frame. Whenever the microprocessor writes to R12 and R13, the
Linear Address Generator is updated at the start of the next vertical frame.
Light Pen Register
On the rising edge of the LPSTB input, after synchronization by two CLK cycles, the value of the Refresh
Memory Address bus is captured by the Light Pen Registers R16 and R17. These registers are readable by-way-
of the microprocessor interface.
Linear Address Generator
The Linear Address Generator generates the Refresh Memory Address. The Linear Address Generator initializes
to the value of the Start Address Registers R12 and R13 at the start of each vertical frame. The Linear Address
Generator remains active during horizontal and vertical retrace, for refresh of dynamic RAMs.
Device Utilization & Performance
Supported
Family
Cyclone
Stratix
Stratix-II
Device
Tested
EP1C20-6
EP1S20-5
EP2S60-3
Utilization
LEs
Memory Memory bits
399
0
0
399
0
0
330
0
0
Performance
F_max
186 MHz
194 MHz
221 MHz
Deliverables
Encrypted Netlist License
• ^{Post synthesis EDIF netlist}
• ^{Assignment & Configuration}
• ^{Symbol & Include files}
• ^Testbench
• ^{Vectors for testing the functionality of the megafunction}
• ^{Place & Route Scripts}
• ^{Documentation}
CAST, Inc.
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