C6845 Datasheet, PDF (4/6 Pages) List of Unclassifed Manufacturers – CRT Controller Megafunction

CAST C6845 Megafunction Datasheet
Horizontal Timing
The Horizontal Timing section consist of the Horizontal Counter, Horizontal Sync Width Counter, Registers R0
through R3, and associated synchronous Set/Reset Flip-Flops and Coincidence Circuits.
The Horizontal Counter counts from zero until coincidence with Register R0 synchronously resets the counter.
This represents the horizontal line rate and enabling of the Display Enable (DE) for a new line takes place.
Coincidence of the Horizontal Counter with Register R1 marks the end of the active display portion of a
horizontal line with Display Enable (DE) going inactive.
Coincidence of the Horizontal Counter with Register R2 marks the beginning of horizontal retrace with
Horizontal Sync (HS) going active high.
Coincidence of the Horizontal Sync Width Counter with Register R3 marks the end of horizontal retrace with
Horizontal Sync (HS) going inactive low.
Vertical Timing
The Vertical Timing section consists of the Scan Line Counter, Character Row Counter, Registers R4 through
R9, the Vertical Control logic block, and associated Coincidence Circuits.
The Scan Line Counter counts from zero until coincidence with Register R9 synchronously resets the Scan Line
Counter and synchronously increments the Character Row Counter. The Scan Line Counter counts the Scan
Lines composing a character row, and the Character Row Counter counts the character rows comprising a
vertical frame.
The Character Row Counter coincidence with R4 and the residual Scan Line count represented by R5 marks the
end of a vertical frame.
The Character Row Counter coincidence with Register R6 marks the end of the active display portion of the
vertical frame measured in character rows.
The Character Row Counter coincidence with Register R7 marks the beginning of vertical retrace with Vertical
Sync (VS) going active high. VS remains high for a fixed period of 16 scan lines.
Register R8, Interlace Mode Register, effects the Vertical Timing according to its programming. Normal Sync
(Non-Interlace) mode displays the same field each frame. Interlace Sync Mode splits a frame into even and
odd fields. Vertical Sync (VS) active high is delayed one-half scan line at the end of even fields. For Interlace
Sync & Video Mode, in addition to the VS delay on even fields, the Row Address counter sequences on even
fields through 0,2,4,… counter values while on odd fields, through 1,3,5,… counter values.
Cursor
The Cursor section consist of the Cursor Control, Cursor Start Register R10, Cursor End Register R11, Cursor
Address Registers R14 and R15, and associated Interlace Mode Register settings and Refresh Memory Address
and Row Address buses as well as associated Coincidence Circuits.
As a first condition for activating the cursor, Cursor Address Registers R14 and R15 signify the character in
linear address space the cursor can be active. Then, Cursor Start Register R10 and Cursor End Register R11
select the scan lines within the designated character space the cursor will be active.
In addition, Cursor Start Register R10 contains a 2-bit field indicating whether the cursor is active or not, and,
if so, whether it should blink or not, and, if blink, at 1/16^th or 1/32^nd the field rate.
CAST, Inc.
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