HM17CM4096 Datasheet, PDF (48/67 Pages) List of Unclassifed Manufacturers – 128XRGBX162 OUTPUT LCD DRIVER IC with built-in RAM

HM17CM4096
(30) INSTRUCTION
INSTRUCTION TABLE (1)
INSTRUCTION
CODE(80 series I/F)
RE flag
Register address
Control address
CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
function
X address(lower)
0 1 1 0 0 0 0 0 0 0 0 AX3 AX2 AX1 AX0 Write in to display RAM
X address(upper)
0 1 1 0 0 0 0 0 0 0 1 * AX6 AX5 AX4
Y address(lower)
Y address(upper)
0 1 1 0 0 0 0 0 0 1 0 AY3 AY2 AY1 AY0
RAM Y
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0 1 1 0 0 0 0 0 0 1 1 AY7 AY6 AY5 AY4
display start line set (lower) 0 1 1 0 0 0 0 0 1 0 0 LA3 LA2 LA1 LA0 RAM Y address setting
corresponds to scan start
display start line set (upper) 0 1 1 0 0 0 0 0 1 0 1 LA7 LA6 LA5 LA4 line of common driver.
N line inversion set (lower) 0 1 1 0 0 0 0 0 1 1 0 N3 N2 N1 N0 _{quantity setting of line}
N line inversion set (upper) 0 1 1 0 0 0 0 0 1 1 1 N7 N6 N5 N4 ^inversion
display control (1)
display control (2)
increment control
power control
SHIFT: common shift direction set,
0
1
1
0
0
0
0
1
0
0
0
SHI
FT
MO
N
ALL ON/ MON: BW/gradation display,
ON OFF ^{ALLON: all on ,}
ON/OFF: display ON/OFF control
REV: display positive / negative,
0
1
1
0
0
0
0
1
0
0
1
REV
NLI
N
SWA
P
REF
NLIN: n line inversion ON/OFF,
SWAP: display data swap,
REF: segment positive / negative
WIN: window selection,
0
1
1
0
0
0
0
1
0
1
0
WIN AIM
AYI
AXI
AIM: increment timing selection,
AYI:Y increment,
AXI:X increment
AMPON: internal OP Amp. ON,
0
1
1
0
0
0
0
1
0
1
1
AMP HAL
ON T
DCO
N
ACL
HALT: power save
DCON: boosting circuit ON, ACL:
reset
LCD duty set
0 1 1 0 0 0 0 1 1 0 0 DS3 DS2 DS1 DS0 LCD driver duty ratio set
boosting coefficient set
0 1 1 0 0 0 0 1 1 0 1 * VU2 VU1 VU0 Boosting times set
bias ratio set
0 1 1 0 0 0 0 1 1 1 0 * B2 B1 B0 LCD drive bias set
RE register set
0 1 1 0 0/1 0/1 0/1 1 1 1 1 TST RE2 RE1 RE0 RE flag set
Notice 1) * mark is Don’t Care
Notice 2) The commands that upper/lower register settings are demanded are effective at the point of commands input.
But electric volume is effective after upper and lower register setting.
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