RFM63B Datasheet, PDF (42/90 Pages) List of Unclassifed Manufacturers – ISM TRANSCEIVER MODULE V1.1

ADVANCED COMMUNICATIONS & SENSING
RFM63B
5.3.3. Rx Processing
If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK
signal is provided.
Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively
on DATA and IRQ_1 pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as
illustrated in Figure 36.
DATA (NRZ)
DCLK
Figure 36: Rx Processing in Continuous Mode
Note that in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal
even if the DCLK signal is not used by the uC. (bit synchronizer is automatically enabled in Buffered and Packet
mode).
5.3.4. Interrupt Signals Mapping
The tables below give the description of the interrupts available in Continuous mode.
IRQ_0
Rx_stby_irq_0
00 (d)
01
1x
IRQ_1
Rx
Sync
RSSI
-
DCLK
Table 17: Interrupt Mapping in Continuous Rx Mode
Note: In Continuous mode, no interrupt is available in Stby mode
IRQ_0
IRQ_1
Table 18: Interrupt Mapping in Continuous Tx Mode
Tx
-
DCLK
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