MINI58LDE Datasheet, PDF (41/83 Pages) List of Unclassifed Manufacturers – 32-bit Microcontroller

MINI58DE
Exception
Number
Interrupt Number
(Bit In Interrupt Interrupt Name
Registers)
35
19
I2C1_INT
36 ~ 40
20 ~ 24
-
41
25
ACMP_INT
42 ~ 43
26 ~ 27
-
44
28
PWRWU_INT
45
46 ~ 47
29
30 ~ 31
ADC_INT
-
Source
Module
I²C1
-
ACMP
-
CLKC
ADC
-
Interrupt Description
I²C1 interrupt
-
Analog Comparator 0 or Comparator 1
interrupt
-
Clock controller interrupt for chip wake-
up from Power-down state
ADC interrupt
-
Power-Down
Wake-Up
No
Yes
Yes
No
Table 6.2-8 System Interrupt Map Vector Table
6.2.8.4 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table
based address is fixed at 0x00000000. The vector table contains the initialization value for the
stack pointer on reset, and the entry point addresses for all exception handlers. The vector
number on previous page defines the order of entries in the vector table associated with the
exception handler entry as illustrated in previous section.
Vector Table Word Offset (Bytes)
0x00
Exception Number * 0x04
Description
Initial Stack Pointer Value
Exception Entry Pointer using that Exception Number
Table 6.2-9 Vector Table Format
6.2.8.5 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending; however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
Dec. 09, 2015
Page 41 of 83
Rev.1.02