NUC945ADN Datasheet, PDF (39/333 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC945ADN
[0]
IDLE
32-BIT ARM926EJ-S BASED MCU
CPU IDLE mode Enable
Setting this bit HIGH, ARM CPU Core enters power saving mode. The
peripherals still working if the clock enable bit in CLKSEL is set. Any nIRQ or
nFIQ to ARM core will let ARM core to exit IDLE state.
1 = CPU IDLE mode enable
0 = Normal mode
IRQ Wakeup Control Register (IRQWAKECON)
Register
Address
IRQWAKECON _{0xB000_0218}
R/W
R/W
Description
IRQ Wakeup Control Register
Reset Value
0x0000_0000
31
30
29
28
27
RESERVED
23
22
21
20
19
RESERVED
15
14
13
12
11
RESERVED
7
6
5
4
3
RESERVED
26
25
24
18
17
16
10
9
8
IRQWAKEUPPOL0
2
1
0
IRQWAKEUPEN0
Bits
Descriptions
[9:8]
IRQWAKEUPPOL0
Wakeup Polarity for nIRQ[1:0]
1 = nIRQx is high level wakeup
0 = nIRQx is low level wakeup
[1:0]
IRQWAKEUPEN0
Wakeup Enable for nIRQ[1:0]
1 = nIRQx wakeup enable
0 = nIRQx wakeup disable
The reserved bit has to keep on logical 0.
Publication Release Date: Jun. 18, 2010
39
Revision: A5