NUC945ADN Datasheet, PDF (193/333 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC945ADN
32-BIT ARM926EJS-BASED MCU
6.8.3 USB Device Control Registers
Interrupt Register (IRQ)
Register
IRQ
Address
0xB000_6000
R/W Description
R
Interrupt Register
Default
Value
0x0000_0000
31
23
15
7
EPF_INT
30
22
14
6
EPE_INT
29
21
13
5
EPD_INT
28
27
Reserved
20
19
Reserved
12
11
Reserved
4
3
EPC_INT EPB_INT
26
18
10
2
EPA_INT
25
17
9
1
CEP_INT
24
16
8
0
USB_INT
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
Descriptions
EPF_INT
This bit conveys the interrupt for Endpoints F.
When set, the corresponding Endpoint F's interrupt status register should be
read to determine the cause of the interrupt.
EPE_INT
This bit conveys the interrupt for Endpoints E.
When set, the corresponding Endpoint E's interrupt status register should be
read to determine the cause of the interrupt.
EPD_INT
This bit conveys the interrupt for Endpoints D.
When set, the corresponding Endpoint D's interrupt status register should be
read to determine the cause of the interrupt.
EPC_INT
This bit conveys the interrupt for Endpoints C.
When set, the corresponding Endpoint C's interrupt status register should be
read to determine the cause of the interrupt.
EPB_INT
This bit conveys the interrupt for Endpoints B.
When set, the corresponding Endpoint B's interrupt status register should be
read to determine the cause of the interrupt.
EPA_INT
This bit conveys the interrupt for Endpoints A.
When set, the corresponding Endpoint A's interrupt status register should be
read to determine the cause of the interrupt.
CEP_INT
Control Endpoint Interrupt.
This bit conveys the interrupt status for control endpoint. When set, Control-
ep’s interrupt status register should be read to determine the cause of the
interrupt.
Publication Release Date: Jun 18, 2010
193
Revision: A5