NEURON6050 Datasheet, PDF (3/4 Pages) List of Unclassifed Manufacturers – IP Processor for IzoTTM Enabled Devices

Enhancements for processing IP packets:
The Neuron 6050 Processor has an enhanced MAC layer
that allows frame sizes up to 1280 bytes that allows large IP
frames to be carried over a variety of channel types without
fragmenting the packet which provides better bandwidth
utilization of the channel. Having dedicated processor
contexts for the MAC and network protocol support allows
the application to have the same performance independent
of the network traffic. Traditional uni-processor designs must
be interrupted repeatedly to receive every packet on the
network, even when the packet turns out to not be addressed
to the node. This increases the demands on the application
processor and makes the amount of processing available to
the application difficult to predict as it becomes a function of
the network load.
JTAG. The Neuron 6050 Processor provides an interface for
the Institute of Electrical and Electronics Engineers (IEEE)
Standard Test Access Port and Boundary-Scan Architecture
(IEEE 1149.1-1990) of the Joint Test Action Group (JTAG) to
allow a Series 6050 chip to be included in the boundary-scan
chain for device production tests.
Communications Port
The Neuron 6050 Processor includes a versatile 5-pin
communications port that can be configured in two ways:
3.3 V Single-Ended Mode and 3.3 V Special-Purpose Mode.
In Single-Ended Mode, pin CP0 is used for receiving serial
data, pin CP1 for transmitting serial data, and pin CP2 for
enabling an external transmitter. Data is communicated using
Differential Manchester encoding.
In Special-Purpose Mode, pin CP0 is used for receiving serial
data, pin CP1 for transmitting serial data, pin CP2 transmits
a bit clock, and pin CP4 transmits a frame clock for use by
an external intelligent transceiver. In this mode, the external
transceiver is responsible for encoding and decoding the data
stream.
Unlike the Neuron 3120/3150 Chips, the Neuron 6050
Processor does not support the Differential Mode
configuration for the communications port. Thus, devices
that require Differential Mode transceiver types must be
redesigned for a Neuron 6050 Processor to use Single-
Ended Mode with external circuitry to provide Single-Ended
to Differential Mode conversions. See the Series 6050 Chip
Data Book and the Connecting a Neuron 6050 Processor
to an External Transceiver Engineering Bulletin for more
information.
Any 3.3V transceiver or a 5V transceiver with TTL-compatible
inputs can be used with the Neuron 6050 Processor because
the communications port has pins that are 5V tolerant and
drive a 3.3V signal. Common transceiver types that can be
used with a Neuron 6050 Processor include twisted-pair, RF,
IR, fiber-optic, and coax.
I/O Pins and Counters
The Neuron 6050 Processor provides 12 bidirectional I/O
pins that are 5V tolerant and can be configured to operate in
one or more of 35 predefined standard input/output models.
The chip also has two 16-bit timer/counters that reduce the
need for external logic and software development.
Memory Architecture
The Neuron 6050 Processor eliminates the need for external
serial EEPROM that the previous generation Neuron 5000
required and instead relies on inexpensive external flash
memories for non-volatile application and data storage, and
for Neuron firmware upgrades. It has 16KB of ROM and 64KB
(44 KB user-accessible) of RAM on the chip. It has no on-chip
non-volatile memory for application use. Each chip, however,
contains its unique identifier (IEEE MAC ID) in an on-chip,
non-volatile, read-only memory. Typical external flash memory
configuration is 512KB of which 128KB is available for
application code. This is a three-fold increase in application
size that can be hosted on the Neuron 6050 compared to
previous generations. Larger application sizes are possible
with larger flashes. For example, a 256KB application is
possible on a 1 MB flash part.
The application code and configuration data are stored in
the external non-volatile memory (NVM) and copied into
the internal RAM during device reset; the instructions then
execute from internal RAM. Writes to NVM are shadowed
in the internal RAM and pushed out to external NVM by the
Neuron 6050 firmware. The application does not manage
NVM directly.
External memories supported. The Neuron 6050 Processor
supports serial peripheral interface (SPI) for accessing off-
chip non-volatile memories.
The Neuron 6050 Processor supports a variety of flash
devices from different manufacturers. Echelon has qualified
the following SPI flash memory devices for use with the
Neuron 6050 Processor:
Winbond W25X40CL 4-Mbit SPI Serial Flash Memory.
Memory map. The Neuron 6050 Processor maps the Neuron
firmware, application code, application data, and system data
to an on-chip 64 KB RAM. The Neuron firmware, application
code, persistent data are loaded from an external serial flash
memory. The application code and persistent data can be up
to 256 KB, and is automatically swapped into and out of the
on-chip RAM by the Neuron firmware.
Programming memory devices. Because the Neuron 6050
Processor does not have any on-chip user-accessible NVM,
only the external flash devices need to be programmed with
the application and configuration data. The memory devices
can be programmed in any of the following ways:
• In-circuit programming on the board.
• Over the network.
• P re-programming before soldering on the board.
Migration Considerations
Most device designs that use the previous-generation Neuron
5000, Neuron 3120 or Neuron 3150 Chip can transition
to using the Neuron 6050 Processor. Because the supply
voltage and memory architecture of Neuron 3120/3150
Chips and Neuron 6050 Processors are different, the
transition requires a hardware re-design of the boards. The
supply voltage of the Neuron 5000 and the Neuron 6050
are the same but they have different memory architectures.
Neuron 5000 designs using external flash could transition