NEURON6050 Datasheet, PDF (1/4 Pages) List of Unclassifed Manufacturers – IP Processor for IzoTTM Enabled Devices

®
Neuron® 6050
IP Processor for IzoT^TM Enabled Devices
Neuron 6050 Key Features
• Upto 80MHz system clock, 64KB
RAM and 16KB ROM on-chip
memories
• Support for larger external
flash memories, up to 256KB
applications
• Support for up to 254 Network
Variables (NVs), 127 aliases
• 16-fold increase in address table
entries, up to 254 entries
• User programmable interrupts,
hardware UART, 12 I/O pins with
35 programmable standard I/O
models
• 5-pin network communications
port with 3.3V drive and
5V-tolerant pins.
• Unique 48-bit IEEE MAC ID
in every device for network
installation and management
• 7mm x 7mm 48-pin QFN
package, -40°C to +85°C
The Neuron 6050 is optimized for
modernizing and consolidating smart
control devices and networks.
It is a key product in Echelon’s
NVM
(SPI)
IzoT™ Platform — the most
comprehensive and open control
networking platform for the Industrial
Internet of Things (IIoT). It offers options for
backward compatibility with LONWORKS^®
while adding native IP addressing at the
device level and consolidating multiple
control protocols on the same device.
The Neuron 6050 Processor incorporates
communication and control functions on
a single chip, in both hardware and
firmware, to facilitate the design of
LonTalk^®, LonTalk/IP or BACnet/IP devices.
Its flexible 5-pin communications port
can be configured to interface with a wide
variety of transceivers — including twisted-
pair, RF, IR, fiber-optics, and coaxial — at a
wide range of data rates.
The Neuron 6050 Processor includes
3 independent 8-bit logical processors
to manage the physical MAC layer, the
network, and the user application. These
are called the Media-Access Control (MAC)
processor, the network (NET) processor,
and the application (APP) processor,
respectively (see Figure 1). At higher system
clock rates, a fourth processor called the
IRQ CPU can be used to handle interrupts.
12
/
I/O
2-6
Serial
/
Memory
Interface
Comm
Port
5
/
External
Transformer
IRQ CPU
RAM
(64K x 8)
APP CPU
NET CPU
ROM
(16K x 8)
MAC CPU
Clock, Reset,
and Service
JTAG
5
Figure 1: Neuron 6050 Processor
Multi-protocol Operation, Future
Proofing and Backward Compatibility
The Neuron 6050 Processor supports up
to four different modes of operation, as
shown in Figure 2, allowing device makers
unprecedented flexibility in creating control
devices for a wide variety of applications
using one common development effort.
Backward compatibility and future proofing
can both be met using a common platform
based on the Neuron 6050 Processor
family.
Preliminary
www.echelon.com