N76E885 Datasheet, PDF (28/196 Pages) List of Unclassifed Manufacturers – Microcontroller

N76E885 Datasheet
8. I/O PORT STRUCTURE AND OPERATION
The N76E885 has a maximum of 26 bit-addressable general I/O pins grouped as 4 ports, P0 to P3.
Each port has its port control register (Px register). The writing and reading of a port control register
have different meanings. A write to port control register sets the port output latch logic value, whereas
a read gets the port pin logic state. All I/O pins except P1.2 can be configured individually as one of
four I/O modes by software. These four modes are quasi-bidirectional (standard 8051 port structure),
push-pull, input-only, and open-drain modes. Each port spends two special function registers PxM1
and PxM2 to select the I/O mode of port Px. The list below illustrates how to select the I/O mode of
Px.n. Note that the default configuration of is input-only (high-impedance) after any reset.
Table 8–1. Configuration for Different I/O Modes
PxM1.n
0
0
1
1
PxM2.n
0
1
0
1
I/O Type
Quasi-bidirectional
Push-pull
Input-only (high-impedance)
Open-drain
All I/O pins can be selected as TTL level inputs or Schmitt triggered inputs by selecting corresponding
bit in PxS register. Schmitt triggered input has better glitch suppression capability. All I/O pins also
have bit-controllable, slew rate select ability via software. The control registers are PxSR. By default,
the slew rate is slow. If user would like to increase the I/O output speed, setting the corresponding bit
in PxSR, the slew rate is selected in a faster level.
There are five I/O pins those support high sink current including P0.1, P0.2, P0.3, P2.0, and P2.1. By
default they have the same sink capability as other I/O pins. By setting PxnSNK, their independent bits
in P1S register, they can be individually configured as high sink capability. It is suitable to drive LED or
large loading without BJT devices. Note that setting PxnSNK bit only increases the sink capability but
the source capability remains the same.
P1.2 is configured as an input-only pin when programming RPD (CONFIG0.2) as 0. Meanwhile, P1.2
is permanent in input-only mode and Schmitt triggered type. P1.2 also has an internal pull-up enabled
by P12UP (P1M2.2). If RPD remains un-programmed, P1.2 pin functions as an external reset pin and
P1.2 is not available. A read of P1.2 bit is always 0. Meanwhile, the internal pull-up is always enabled.
8.1 Quasi-Bidirectional Mode
The quasi-bidirectional mode, as the standard 8051 I/O structure, can rule as both input and output.
When the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low.
Dec. 21, 2015
Page 28 of 196
Rev. 1.01