FEDL9042-01 Datasheet, PDF (27/58 Pages) List of Unclassifed Manufacturers – DOT MATRIX LCD CONTROLLER DRIVER

LAPIS Semiconductor
FEDL9042-01
ML9042-xx
I/F with CPU
Parallel interface mode
The ML9042 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit
microcontroller (CPU).
1) 8-bit interface data length
The ML9042 uses all of the 8 data bus lines DB₀(SO) to DB₇ at a time to transfer data to and from the CPU.
2) 4-bit interface data length
The ML9042 uses only the higher-order 4 data bus lines DB₄ to DB₇ twice to transfer 8-bit data to and from the
CPU.
The ML9042 first transfers the higher-order 4 bits of 8-bit data (DB₄ to DB₇ in the case of 8-bit interface data
length) and then the lower-order 4 bits of the data (DB₀(SO) to DB₃ in the case of 8-bit interface data length).
The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4
bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is
made, the following data transfer cannot be completed properly.
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