LM3S301 Datasheet, PDF (252/373 Pages) List of Unclassifed Manufacturers – Microcontroller

Universal Asynchronous Receiver/Transmitter (UART)
Register 12: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
Offset 0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OEIC BEIC PEIC FEIC RTIC TXIC RXIC
reserved
Type
RO
RO
RO
RO
RO
W1C
W1C
W1C
W1C
W1C
W1C
W1C
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:11
10
9
8
7
6
5
4
3:0
Name
reserved
OEIC
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
reserved
Type
RO
W1C
W1C
W1C
W1C
W1C
W1C
W1C
RO
Reset
0
0
0
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
Overrun Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Break Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Parity Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Framing Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Receive Time-Out Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Transmit Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Receive Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Reserved bits return an indeterminate value, and should never
be changed.
252
October 6, 2006
Preliminary