LM3S801 Datasheet, PDF (248/397 Pages) List of Unclassifed Manufacturers – Microcontroller

Synchronous Serial Interface (SSI)
12.4
3. Write the SSICPSR register with a value of 0x00000002.
4. Write the SSICR0 register with a value of 0x000009C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
Register Map
Table 12-1 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s
address, relative to the SSI base address of 0x40008000.
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the
control registers are reprogrammed.
Table 12-1. SSI Register Map
Offset Name
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0xFD0
0xFD4
0xFD8
0xFDC
0xFE0
0xFE4
0xFE8
0xFEC
0xFF0
0xFF4
0xFF8
0xFFC
SSICR0
SSICR1
SSIDR
SSISR
SSICPSR
SSIIM
SSIRIS
SSIMIS
SSIICR
SSIPeriphID4
SSIPeriphID5
SSIPeriphID6
SSIPeriphID7
SSIPeriphID0
SSIPeriphID1
SSIPeriphID2
SSIPeriphID3
SSIPCellID0
SSIPCellID1
SSIPCellID2
SSIPCellID3
Reset
Type Description
0x00000000
0x00000000
0x00000000
0x00000003
0x00000000
0x00000000
0x00000008
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000022
0x00000000
0x00000018
0x00000001
0x0000000D
0x000000F0
0x00000005
0x000000B1
RW
RW
RW
RO
RW
RW
RO
RO
W1C
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Control 0
Control 1
Data
Status
Clock prescale
Interrupt mask
Raw interrupt status
Masked interrupt status
Interrupt clear
Peripheral identification 4
Peripheral identification 5
Peripheral identification 6
Peripheral identification 7
Peripheral identification 0
Peripheral identification 1
Peripheral identification 2
Peripheral identification 3
PrimeCell identification 0
PrimeCell identification 1
PrimeCell identification 2
PrimeCell identification 3
See
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October 8, 2006
Preliminary