PS20353 Datasheet, PDF (24/27 Pages) List of Unclassifed Manufacturers – Nordig Unified DVB-T COFDM Terrestrial Demodulator

PS20353
4.5.1.3
Calculating Crystal Power Dissipation
To calculate the power dissipated in a crystal the following equation can be used.
Pc = power dissipated in crystal at resonant frequency (W)
Vpp = maximum peak to peak output swing of amplifier is 1.8V for all CVdd
Zin = crystal network impedance (see Equation 2)
4.5.1.4
Capacitor Values
Using the loop gain limits (5 < A < 25), the maximum and minimum values for C1 and C2 can be calculated with
Equation 4 below.
Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2.
Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that the
resulting crystal load capacitance CL (see Equation 5) is close to the crystal manufacturers recommended CL
(standard values for CL are 15pF, 20pF and 30pF). The crystal will then operate very near its specified frequency.
Cpar12 = parasitic capacitance between the XTI and XTO pins. It consists of the IC package’s pin-to-pin
capacitance (including any socket used) and the printed circuit board’s track-to-track capacitance.
Cpar12 ≈ 2pF.
If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer’s
recom-mended CL may be acceptable. Larger values of CL tend to reduce the influence of circuit variations and
tolerances on frequency stability. Smaller values of C _L tend to reduce startup time and crystal power dissipation.
Care must however be taken that CL does not fall outside the crystal pulling range or the circuit may fail to start up
altogether. It is also possible to quote CL to the crystal manufacturer who can then cut a crystal to order which will
resonate, under the specified load conditions, at the desired frequency.
Finally the power dissipation in the crystal must be checked. If Pc is too high C1 and C2 must be reduced. If this is
not feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain
condition is still satisfied. This must be done using Equation 1.
4.5.1.5
Oscillator/Clock Application Notes
• On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible. Other
signal tracks must not be allowed to cross through this area. The component tracks should preferably be ringed
by a ground track connected to the chip ground (0V) on adjacent pins either side of the crystal pins. It is also
advisable to provide a ground plane for the circuit to reduce noise.
• External clock signals, applied to XTI and/or XTO, must not exceed the cell supply limits (i.e., 0V and CVdd)
and current into or out of XTI and/or XTO must be limited to less than 10mA to avoid damaging the cell’s
amplitude clamping circuit.
• An external, DC coupled, single ended square wave clock signal may be applied to XTI if OSCMODE = 0. To
limit the current taken from the signal source a resistor should be placed between the clock source and XTI.
The recommended value for this series resistor is 470 Ω for a clock signal switching between 0V and CVdd.
The current the clock source needs to source/sink is then ≤ 1.9 mA. The XTO pin must be left unconnected in
this configuration. See Figure 15.
• AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty cycle of the
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