NUC502 Datasheet, PDF (24/266 Pages) List of Unclassifed Manufacturers – 32-bit Microprocessor

NUC502
6 Functional Description
6.1 ARM7TDMI CPU Core
The ARM7TDMI CPU core, a member of the Advanced RISC Machines (ARM) family of
general-purpose 32-bit microprocessors, offers high performance with very low power
consumption. The architecture is based on Reduced Instruction Set Computer (RISC)
principles, and the instruction set and related decode mechanism are much simpler than
those of micro-programmed Complex Instruction Set Computers. Pipelining is employed so
that all parts of the processing and memory systems can operate continuously. The high
instruction throughput and impressive real-time interrupt response are the major benefits.
The ARM7TDMI CPU core has two instruction sets:
(1) The standard 32-bit ARM code
(2) 16-bit THUMB code
The THUMB code is 16-bit instruction set that allows it to increase the code density
compare to standard ARM core while retaining most of the ARM performance advantage
over a traditional 16-bit processor using 16-bit registers. THUMB instructions operate with
the standard ARM register configuration, allowing excellent interoperability between ARM
and THUMB states. Each 16-bit THUMB instruction has a corresponding 32-bit ARM
instruction with the same effect on the processor model.
ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 registers are visible;
the other registers are used to speed up exception processing. All the register specifies in
ARM instructions can address any of the 16 registers. The CPU also supports 5 types of
exception, such as two levels of interrupt, memory aborts, attempted execution of an
undefined instruction and software interrupts.
Apr 30, 2015
Page 24 of 266
Rev 1.1