NUC502 Datasheet, PDF (160/266 Pages) List of Unclassifed Manufacturers – 32-bit Microprocessor

NUC502
Command Register (CMDR)
Register Offset
R/W/C Description
CMDR
0x08
R/W Command Register
Reset Value
0x0000_000x
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
START
STOP
READ
WRITE
ACK
NOTE: Software can write this register only when I2C_EN = 1.
Bits
Descriptions
[31:5] Reserved
Reserved
[4]
START
Generate Start Condition
Generate (repeated) start condition on I²C bus when this bit set 1.
[3]
STOP
Generate Stop Condition
Generate stop condition on I²C bus when this bit set 1.
[2]
READ
Read Data From Slave
Retrieve data from slave when this bit set 1.
[1]
WRITE
Write Data To Slave
Transmit data to slave when this bit set 1.
[0]
ACK
Send Acknowledge To Slave
When I²C behaves as a receiver, sent ACK (ACK = ‘0’) or NACK (ACK = ‘1’) to
slave.
NOTE: The START, STOP, READ and WRITE bits are cleared automatically while transfer
finished. READ and WRITE cannot be set concurrently.
Apr 30, 2015
Page 160 of 266
Rev 1.1