RFM12B_15 Datasheet, PDF (21/41 Pages) List of Unclassifed Manufacturers – Universal ISM Band FSK Transceiver

RFM12B
Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
Bit 0 (dr): Disables the highly sensitive RESET mode.
dr
Reset mode
0
Sensitive reset
1
Non-sensitive reset
Reset triggered when
V_dd below 1.6V, V_dd glitch greater than 600mV
V_dd below 250mV
Note: To restart the synchron pattern recognition, bit 1 (ef, FIFO fill enable) should be cleared and set.
8. Synchron Pattern Command
Bit 15 14 13 12 11 10 9
1100111
876543210
0 b7 b6 b5 b4 b3 b2 b1 b0
POR
CED4h
The Byte0 of the synchron pattern (see FIFO and Reset Mode command) can be reprogrammed by B <b7:b0>.
9. Receiver FIFO Read Command
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1011000000000000
POR
B000h
With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command
.
Note: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the duty-cycle of the
clock signal is not 50 % the shorter period of the clock pulse width should be at least 2/fref.
10. AFC Command
Bit 15 14 13 12 11 10 9
1100010
876543
0 a1 a0 rl1 rl0 st
210
fi oe en
POR
C4F7h
Bit 7-6 (a1 to a0): Automatic operation mode selector:
a1 a0
00
01
10
11
Operation mode
Auto mode off (Strobe is controlled by microcontroller)
Runs only once after each power-up
Keep the f_offset only during receiving (VDI=high)
Keep the f_offset value independently from the state of the VDI signal
21
Tel: [phone] Fax: [phone] E-mail: [e-mail] http://www.hoperf.com