SLN08G72G2BA2HY-CCRT Datasheet, PDF (2/17 Pages) List of Unclassifed Manufacturers – 8GB DDR3L – SDRAM ECC SO-DIMM

preliminary Data Sheet
Rev.0.9 03.06.2013
This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM ECC Small Outline Dual-In-line
Memory Module (SO-UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses
internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to
achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ
and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. The burst length is either four or
eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated
at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent
operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-
down” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I²C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
1G x 72bit
DDR3 SDRAMs used
18 x 512M x 8bit (4Gbit)
Row
Addr.
16
Device Bank
Addr.
Column
Addr.
Refresh
Module
Bank Select
BA0, BA1, BA2 10
8k
S0#, S1#
Module Dimensions
in mm
67.60 (long) x 30(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
SLN08G72G2BA2HY-CCRT
SLN08G72G2BA2HY-DCRT
Module Density Transfer Rate Clock Cycle/Data bit rate Latency
8GByte
10.6 GB/s
1.5ns/1333MT/s
9-9-9
8GByte
12.8 GB/s
1.25ns/1600MT/s
11-11-11
Pin Name
A0 – A9, A11 – A15
A10/AP
BA0 – BA2
DQ0 – DQ63
CB0 – CB07
DM0 – DM8
DQS0 – DQS8
DQS0# – DQS8#
RAS#
CAS#
WE#
CKE0 – CKE1
S0#, S1#
CK0 – CK1
CK0# – CK1#
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
ECC check bits
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Chip Select
Clock Inputs, positive line
Clock Inputs, negative line
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
Page 2
of 17