SGU02G64A1BD1SA-BBR Datasheet, PDF (2/16 Pages) List of Unclassifed Manufacturers – 2048MB DDR3 . SDRAM UDIMM

Data Sheet
Rev.1.0 12.04.2013
This Swissbit module is an industry standard 240-pin 8-byte DDR3 SDRAM Dual-In-line Memory Module
(UDIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured
octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed
operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses
to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I²C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization DDR3 SDRAMs used
256M x 64bit 8 x 256M x 8bit (2048Mbit)
Row
Addr.
15
Device Bank
Addr.
BA0, BA1, BA2
Col.
Addr.
10
Refresh
8k
Module
Bank Select
S0#
Module Dimensions
in mm
133.35 (long) x 30(high) x 2.70[max] (thickness)
Timing Parameters
Part Number
SGU02G64A1BD1SA-BBR
SGU02G64A1BD1SA-CCR
SGU02G64A1BD1SA-DCR
Module Density Transfer Rate
2048 MB
8.5 GB/s
2048 MB
10.6 GB/s
2048 MB
12.8 GB/s
Clock Cycle/Data bit rate
1.87ns/1066MT/s
1.5ns/1333MT/s
1.25ns/1600MT/s
Latency
7-7-7
9-9-9
11-11-11
Pin Name
A0 – A9, A11 – A14
A10/AP
BA0, BA1, BA2
DQ0 – DQ63
DM0 – DM7
RAS#
CAS#
WE#
CKE0
CK0
CK0#
DQS0 – DQS7
DQS0# - DQS7#
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
Input Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Inputs, positive line
Clock Inputs, negative line
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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