SEP04G72G1AH2MT-30R Datasheet, PDF (2/16 Pages) List of Unclassifed Manufacturers – 4GB DDR2 . SDRAM registered DIMM

Data Sheet
Rev.1.2 14.02.2014
This Swissbit module is an industry standard 240-pin 8-byte DDR2 SDRAM Dual-In-line Memory Module (DIMM)
which is organized as x72 high speed CMOS memory arrays. The module uses internally configured quad-bank
DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-speed operation. DDR2
SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR2
SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of
locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge
function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The
DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high
effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All inputs and all
full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I²C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
512M x 72bit
DDR2 SDRAMs used
36 x 256M x 4bit (1Gbit)
Row
Addr.
14
Device Bank
Select
BA0, BA1, BA2
Column
Addr.
11
Refresh
Module
Bank Select
8k
S0#, S1#
Module Dimensions
in mm
133.33 (long) x 30(high) x 4 [max] (thickness)
Timing Parameters
Part Number
SEP04G72G1AH2MT-30R
SEP04G72G1AH2MT-25R
Module Density
4GByte
4GByte
Transfer Rate
5.3 GB/s
6.4 GB/s
Clock Cycle/Data bit
rate
3.0ns/667MT/s
2.5ns/800MT/s
Latency
5-5-5
6-6-6
Pin Name
A0 – A13
BA0, BA1, BA2
DQ0 – DQ63
CB0 – CB7
DM0 – DM8
RAS#
CAS#
WE#
CKE0 – CKE1
CK0 – CK1
CK0# – CK1#
DQS0 – DQS17
DQS0# – DQS17#
S0# – S1#
Address Inputs
Bank Address Inputs
Data Input / Output
Check Bits
Input Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Input, positive line
Clock Input, negative line
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Chip Select
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
Page 2
of 16