NUC501 Datasheet, PDF (191/283 Pages) List of Unclassifed Manufacturers – 32-bit RISC CPU

NUC501
Capture Control Register (CCR0)
Register
Offset
R/W
Description
CCR0 PWM_BA+0x050 R/W Capture Control Register
Reset Value
0x0000_0000
31
23
CFLRD1
15
7
CFLRD0
30
22
CRLRD1
14
6
CRLRD0
29
21
Reserved
13
5
Reserved
28
27
Reserved
20
19
CIIR1 CAPCH1EN
12
11
Reserved
4
3
CIIR0 CAPCH0EN
26
18
FL&IE1
10
2
FL&IE0
25
17
RL&IE1
9
1
RL&IE0
24
16
INV1
8
0
INV0
Bits
[31:24]
Descriptions
Reserved
[23]
CFLRD1
[22]
[21]
CRLRD1
Reserved
[19]
CAPCH1EN
[18]
FL&IE1
[17]
RL&IE1
Reserved
CFLR1 dirty bit
When input channel 1 has a rising transition, CFLR1 was updated and this
bit was “1”.
CRLR1 dirty bit
When input channel 1 has a falling transition, CRLR1 was updated and this
bit was “1”.
Reserved
Capture Channel 1 transition Enable/Disable
1: Enable
0: Disable
When Enable, Capture latched the PMW-counter and saved to CRLR (Rising
latch) and CFLR (Falling latch).
When Disable, Capture does not update CRLR and CFLR, and disable
Channel 1 Interrupt.
Channel1 Falling Interrupt Enable ON/OFF
1: Enable
0: Disable
When Enable, if Capture detects Channel 1 has falling transition, Capture
issues an Interrupt.
Channel 1 Rising Interrupt Enable ON/OFF
1: Enable
0: Disable
Nuvoton Technology Corp.
191
http://www.nuvoton.com/
Revision A1.5