NUC501 Datasheet, PDF (157/283 Pages) List of Unclassifed Manufacturers – 32-bit RISC CPU

NUC501
6.12 I2C Synchronous Serial Interface
6.12.1 Overview
I²C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I²C standard is a multi-master bus with integrated addressing and data-
transfer protocols. It includes collision and arbitration loses detection that prevents data corruption if two
or more masters attempt to control the bus simultaneously.
Serial, 8-bit oriented bi-directional data transfers can be made up to 100k bit/s in Standard-mode, up
to 400k bit/s in the Fast-mode.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-
byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being
transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high
period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be
held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a
command (START or STOP).
6.12.2 Feature
The I²C Master Core includes the following features:
• AMBA APB interface compatible
• Compatible with Philips I²C standard, support master mode
• Multi Master Operation
• Clock stretching and wait state generation
• Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer
• Software programmable acknowledge bit
• Arbitration lost interrupt, with automatic transfer cancellation
• Start/Stop/Repeated Start/Acknowledge generation
• Start/Stop/Repeated Start detection
• Bus busy detection
• Supports 7 bit addressing mode
• Fully static synchronous design with one clock domain
• Software mode I²C
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Revision A1.5