W77L516A Datasheet, PDF (19/89 Pages) List of Unclassifed Manufacturers – 8-BIT MICROCONTROLLER

W77L516A
P4.2 BASE ADDRESS LOW BYTE REGISTER
Bit:
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Mnemonic: P42AL
Address: 9Ah
P4.2 BASE ADDRESS HIGH BYTE REGISTER
Bit:
7
6
5
4
3
2
1
0
A15 A14 A13 A12 A11 A10
A9
A8
Mnemonic: P42AH
Address: 9Bh
P4.3 BASE ADDRESS LOW BYTE REGISTER
Bit:
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Mnemonic: P43AL
Address: 9Ch
P4.3 BASE ADDRESS HIGH BYTE REGISTER
Bit:
7
6
5
4
3
2
1
0
A15 A14 A13 A12 A11 A10
A9
A8
Mnemonic: P43AH
Address: 9Dh
ISP CONTROL REGISTER
Bit:
7
6
5
4
3
2
1
0
SWRST/HWB -
LDAP
-
-
- LDSEL ENP
Mnemonic: CHPCON
Address: 9Fh
SWRST/HWB: Set this bit to launch a whole device reset that is same as asserting high to RST pin,
micro controller will be back to initial state and clear this bit automatically. To read this
bit, its alternate function to indicate the ISP hardware reboot mode is invoking when
read it in high.
LDAP: This bit is Read Only. High: device is executing the program in LDFLASH. Low: device is
executing the program in APFLASHs.
LDSEL: Loader program residence selection. Set to high to route the device fetching code from
LDFLASH.
ENP: In System Programming Mode Enable. Set this be to launch the ISP mode. Device will operate
ISP procedures, such as Erase, Program and Read operations, according to correlative SFRs
settings. During ISP mode, device achieves ISP operations by the way of IDLE state. In the other
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Publication Release Date: December 4, 2008
Revision A9