VS1011E Datasheet, PDF (18/49 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

VLSI
Solution ^y
VS1011e
VS1011E
7. SPI BUSES
SDI Pin
-
BSYNC
DCLK
SDATA
-
SCI Pin
XCS
-
SCK
SI
SO
Description
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. There is no chip select for SDI, which
is always active.
SDI data is synchronized with a rising edge of BSYNC.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. SI is sampled on the rising SCK edge, if XCS is low.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
7.3 Serial Protocol for Serial Data Interface (SDI)
7.3.1 General
The serial data interface operates in slave mode so the DCLK signal must be generated by an external
circuit.
Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.6).
VS1011e assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or
LSb first, depending of contents of SCI MODE (Chapter 8.6).
7.3.2 SDI in VS1002 Native Modes (New Mode)
In VS1002 native modes (which are available also in VS1011e), byte synchronization is achieved by
XDCS (or XCS if SM SDISHARE is 1). The state of XDCS (or XCS) may not change while a data
byte transfer is in progress. To always maintain data synchronization even if there may be glitches in
the boards using VS1011e, it is recommended to turn XDCS (or XCS) every now and then, for instance
once after every flash data block or a few kilobytes, just to keep sure the host and VS1011e are in sync.
For new designs, using VS1002 native modes are recommended, as they are easier to implement than
BSYNC generation.
7.3.3 SDI in VS1001 Compatibility Mode
When VS1011e is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure
correct bit-alignment of the input bitstream. The first DCLK sampling edge (rising or falling, depending
on selected polarity), during which the BSYNC is high, marks the first bit of a byte (LSB, if LSB-first
Version 1.04, 2007-10-08
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