KAD5610P Datasheet, PDF (17/28 Pages) List of Unclassifed Manufacturers – Dual 10-Bit, 250/210/170/125MSPS A/D Converter

KAD5610P
Digital Outputs
Output data is available as a parallel bus in LVDS-
compatible or CMOS modes. In either case, the data
is presented in double data rate (DDR) format with
the A and B channel data available on alternating
clock edges. When CLKOUT is low channel A data is
output, while on the high phase channel B data is
presented. Figures 1 and 2 show the timing relation-
ships for LVDS and CMOS modes, respectively.
Additionally, the drive current for LVDS mode can be
set to a nominal 3 mA or a power-saving 2 mA. The
lower current setting can be used in designs where
the receiver is in close physical proximity to the ADC.
The applicability of this setting is dependent upon the
PCB layout, therefore the user should experiment to
determine if performance degradation is observed.
The output mode and LVDS drive current are se-
lected via the OUTMODE pin as shown in Table 2.
OUTMODE Pin
AVSS
Float
AVDD
Mode
LVCMOS
LVDS, 3 mA
LVDS, 2 mA
Table 2. OUTMODE Pin Settings
The output mode can also be controlled through the
SPI port, which overrides the OUTMODE pin setting.
Details on this are contained in the Serial Peripheral
Interface section.
An external resistor creates the bias for the LVDS driv-
ers. A 10kΩ, 1% resistor must be connected from the
RLVDS pin to OVSS.
Power Dissipation
The power dissipated by the KAD5610P is primarily
dependent on the sample rate, but is also related to
the input signal in CMOS output mode. There is a
static bias in the analog supply, while the remaining
power dissipation is linearly related to the sample
rate. The output supply dissipation is approximately
constant in LVDS mode, but linearly related to the
clock frequency in CMOS mode. Figures 35 and 36
illustrate these relationships.
TBD
Figure 35. Power vs. Sample Rate, LVDS Mode
TBD
Figure 36. Power vs. Sample Rate, CMOS Mode
Nap/Sleep
Portions of the device may be shut down to save
power during times when operation of the ADC is not
required. Two power saving modes are available:
nap, and sleep. Nap mode reduces power dissipa-
tion to 40mW and recovers to normal operation in
approximately 1µs. Sleep mode reduces power dissi-
pation to 10mW but requires 1ms to recover. The
clock should remain running and at a fixed fre-
quency during Nap or Sleep. Recovery time from
Nap mode will increase if the clock is stopped, since
the internal DLL can take up to 52µs to regain lock at
250MSPS.
By default after the device is powered on, the nap
and sleep state is controlled by the NAPSLP pin as
shown in Table 3.
NAPSLP Pin
AVSS
Float
AVDD
Mode
Normal
Sleep
Nap
Table 3. NAPSLP Pin Settings
Rev 0.5.1 Preliminary
Page 17