KAD5610P Datasheet, PDF (16/28 Pages) List of Unclassifed Manufacturers – Dual 10-Bit, 250/210/170/125MSPS A/D Converter

KAD5610P
tails on this are contained in the Serial Peripheral In-
terface section.
A delay-locked loop (DLL) generates internal clock
signals for various stages within the charge pipeline. If
the frequency of the input clock changes, the DLL
may take up to 52µs to regain lock at 250MSPS. The
lock time is inversely proportional to the sample rate.
Figure 32. Differential Amplifier Input
A differential amplifier, as shown in Figure 32, can be
used in applications that require dc-coupling. In this
configuration the amplifier will typically dominate the
achievable SNR and distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure
47). Driving these inputs with a high level (up to 1.8VPP
on each input) sine or square wave will provide the
lowest jitter performance. A transformer with 4:1 im-
pedance ratio will provide increased drive levels.
The recommended drive circuit is shown in Figure 33.
The clock can be driven single-ended, but this will
reduce the edge rate and may impact SNR perform-
ance. The clock inputs are internally self-biased to
AVDD/2 to facilitate ac coupling.
Jitter
In a sampled data system, clock jitter directly im-
pacts the achievable SNR performance. The theoreti-
cal relationship between clock jitter (tJ) and SNR is
shown in Equation 1 and is illustrated in Figure 34.
SNR
=
20
log
10
⎜⎜⎝⎛
1
2 π f_IN
t
J
⎟⎟⎠⎞
Equation 1.
100
95
90
85
80
75
70
65
60
55
50
1
tj=0.1ps
tj=1ps
tj=100ps
tj=10ps
10
100
Input Frequency - MHz
14 Bits
12 Bits
10 Bits
1000
Figure 33. Recommended Clock drive
A selectable 2X/4X divider is provided in series with
the clock input. The divider can be used in the 2X
mode with a sample clock equal to twice the desired
sample rate. This will result in a clock input with 50%
duty cycle and will maximize the converter’s perform-
ance.
CLKDIV Pin
AVSS
Float
AVDD
Divide Ratio
2
1
4
Table 1. CLKDIV Pin Settings
The clock divider can also be controlled through the
SPI port, which overrides the CLKDIV pin setting. De-
Figure 34. SNR vs. Clock Jitter
This relationship shows the SNR that would be
achieved if clock jitter were the only non-ideal fac-
tor. In reality, achievable SNR is limited by internal
factors such as linearity, aperture jitter and thermal
noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure 1. The internal aper-
ture jitter combines with the input clock jitter in a root-
sum-square fashion, since they are not statistically
correlated, and this determines the total jitter in the
system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference pro-
vides the reference charges used in the successive
approximation operations. The full-scale range of
each A/D is proportional to the reference voltage.
The nominal value of the voltage reference is 1.25V.
Rev 0.5.1 Preliminary
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