RFM01 Datasheet, PDF (16/31 Pages) List of Unclassifed Manufacturers – Universal ISM Band FSK Receiver

RFM01
9. Data Rate Command
bit 15 14 13 12 11 10 9
1100100
876543210
0 cs r6 r5 r4 r3 r2 r1 r0
POR
C823h
The expected bit rate of the received data stream is determined by the 7-bit value R (bits r6 to r0) and the 1 bit cs.
BR = 10 MHz / 29 / (R+1) / (1 + cs*7)
In the receiver set R according the next function:
R= (10 MHz / 29 / (1 + cs*7)/ BR) – 1
Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
Data rate accuracy requirements:
Clock recovery in slow mode: ΔBR/BR < 1/(29*Nbit)
Clock recovery in fast mode: ΔBR/BR<3/(29*Nbit)
BR is the bit rate set in the receiver and ΔBR is bit rate difference between the transmitter and the receiver. N is the maximal number of
bit
consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and be
careful to use the same division ratio in the receiver and in the transmitter.
ΔBR is a theoretical limit for the clock recovery circuit. Clock recovery will not work above this limit. The clock recovery circuit will always
operate below this limit independently from process, temperature, or Vdd condition.
Supposing a maximum length of consecutive zeros or ones in the data stream is less than 5 bits, the necessary relative accuracy is 0.68% in
slow mode and 2.1% in fast mode.
10. Output and FIFO Mode Command
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 f3 f2 f1 f0 s1 s0 ff fe
POR
CE85h
Bit 4-7 <f3 : f0>: FIFO IT level. The FIFO generates IT when number of the received data bits reaches this level.
Bit 2-3 <s1 : s0>: Set the input of the FIFO fill start condition:
s1 s0 FIFO fill start condition
0 0 VDI
0 1 Sync Word
1 0 Reserved
1 1 Always
Note: VDI (Valid Data Indicator) see further details in Receiver Control Word, Synchron word in microcontroller mode is 2DD4h.
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