QT60240-ATG Datasheet, PDF (15/26 Pages) List of Unclassifed Manufacturers – 16 AND 24 KEY QMATRIX TOUCH SENSOR ICs

5 I²C Operation
5.1 Interface Bus
More detailed information about I²C is available from
www.i2C-bus.org. Devices are connected onto the I ²C bus as
shown in Figure 5.1. Both bus lines are connected to V dd via
pull-up resistors. The bus drivers of all I ²C devices must be
open-drain type. This implements a wired-AND function which
allows any and all devices to drive the bus, one at a time. A
low level on the bus is generated when a device outputs a
zero.
Figure 5.1 I²C Interface Bus
Vcc
5.3 START and STOP Conditions
The host initiates and terminates a data transmission. The
transmission is initiated when the host issues a START
condition on the bus, and is terminated when the host issues
a STOP condition. Between START and STOP conditions, the
bus is considered busy. As shown below, START and STOP
conditions are signaled by changing the level of the SDA line
when the SCL line is high.
Figure 5.3 START and STOP Conditions
SDA
Device 1 Device 2 Device 3
Device n R1
R2
SDA
SCL
Table 5.1 I²C Bus Specifications
Parameter
Address space
Maximum bus speed (SCL)
Hold time START condition
Setup time for STOP condition
Bus free time between a STOP and START
condition
Unit
7-bit
100 kHz
4µs minimum
4µs minimum
4.7µs minimum
5.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a
pulse on the clock line. The level of the data line must be
stable when the clock line is high; The only exception to this
rule is for generating START and STOP conditions.
Figure 5.2 Data Transfer
SCL
START
STOP
5.4 Address Packet Format
All address packets are 9 bits long, consisting of 7 address
bits, one READ/WRITE control bit and an acknowledge bit. If
the READ/WRITE bit is set, a read operation is performed,
otherwise a write operation is performed. When the device
recognizes that it is being addressed, it will acknowledge by
pulling SDA low in the ninth SCL (ACK) cycle. An address
packet consisting of a slave address and a READ or a
WRITE bit is called SLA+R or SLA+W, respectively.
The most significant bit of the address byte is transmitted
first. The address sent by the host must be consistent with
that selected with the option jumpers.
Figure 5.4 Address Packet Format
SDA
Addr MSB
Addr LSB R/W ACK
SCL
START
1
2
7
8
9
SDA
SCL
Data Stable
Data Stable
Data Change
5.5 Data Packet Format
All data packets are 9 bits long, consisting of one data byte
and an acknowledge bit. During a data transfer, the host
generates the clock and the START and STOP conditions,
while the Receiver is responsible for acknowledging the
reception. An acknowledge (ACK) is signaled by the Receiver
pulling the SDA line low during the ninth SCL cycle. If the
Receiver leaves the SDA line high, a NACK is signaled.
lQ
15
QT60240-ISG R8.06/0906